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[/] [thor/] [trunk/] [rtl/] [verilog/] [Thor_divider.v] - Diff between revs 3 and 13

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Rev 3	Rev 13
Line 1...	Line 1...
`// ============================================================================`	`// ============================================================================`
`// __`	`// __`
`// \\__/ o\ (C) 2013 Robert Finch, Stratford`	`// \\__/ o\ (C) 2013,2015 Robert Finch, Stratford`
`// \ __ / All rights reserved.`	`// \ __ / All rights reserved.`
`// \/_// robfinch<remove>@finitron.ca`	`// \/_// robfinch<remove>@finitron.ca`
`// \|\|`	`// \|\|`
`//`	`//`
`// This source file is free software: you can redistribute it and/or modify`	`// This source file is free software: you can redistribute it and/or modify`
Line 23...	Line 23...
`// Thor_divider.v`	`// Thor_divider.v`
`// - 64 bit divider`	`// - 64 bit divider`
`//`	`//`
`// ============================================================================`	`// ============================================================================`
`//`	`//`
`module Thor_divider(rst, clk, ld, sgn, isDivi, a, b, imm, qo, ro, dvByZr, done);`	`module Thor_divider(rst, clk, ld, abort, sgn, isDivi, a, b, imm, qo, ro, dvByZr, done, idle);`
`parameter WID=64;`	`parameter WID=64;`
`parameter DIV=3'd3;`	`parameter DIV=3'd3;`
`parameter IDLE=3'd4;`	`parameter IDLE=3'd4;`
`parameter DONE=3'd5;`	`parameter DONE=3'd5;`
`input clk;`	`input clk;`
`input rst;`	`input rst;`
`input ld;`	`input ld;`
	`input abort;`
`input sgn;`	`input sgn;`
`input isDivi;`	`input isDivi;`
`input [WID-1:0] a;`	`input [WID-1:0] a;`
`input [WID-1:0] b;`	`input [WID-1:0] b;`
`input [WID-1:0] imm;`	`input [WID-1:0] imm;`
`output [WID-1:0] qo;`	`output [WID-1:0] qo;`
`reg [WID-1:0] qo;`	`reg [WID-1:0] qo;`
`output [WID-1:0] ro;`	`output [WID-1:0] ro;`
`reg [WID-1:0] ro;`	`reg [WID-1:0] ro;`
`output done;`	`output done;`
	`output idle;`
`output dvByZr;`	`output dvByZr;`
`reg dvByZr;`	`reg dvByZr;`

`reg [WID-1:0] aa,bb;`	`reg [WID-1:0] aa,bb;`
`reg so;`	`reg so;`
`reg [2:0] state;`	`reg [2:0] state;`
`reg [7:0] cnt;`	`reg [7:0] cnt;`
`wire cnt_done = cnt==8'd0;`	`wire cnt_done = cnt==8'd0;`
`assign done = state==DONE;`	`assign done = state==DONE;`
	`assign idle = state==IDLE;`
`reg ce1;`	`reg ce1;`
`reg [WID-1:0] q;`	`reg [WID-1:0] q;`
`reg [WID:0] r;`	`reg [WID:0] r;`
`wire b0 = bb <= r;`	`wire b0 = bb <= r;`
`wire [WID-1:0] r1 = b0 ? r - bb : r;`	`wire [WID-1:0] r1 = b0 ? r - bb : r;`
Line 76...	Line 79...
`cnt <= 8'd0;`	`cnt <= 8'd0;`
`state <= IDLE;`	`state <= IDLE;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`if (!cnt_done)`	`if (abort)`
	`cnt <= 8'd00;`
	`else if (!cnt_done)`
`cnt <= cnt - 8'd1;`	`cnt <= cnt - 8'd1;`

`case(state)`	`case(state)`
`IDLE:`	`IDLE:`
`if (ld) begin`	`if (ld) begin`

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[/] [thor/] [trunk/] [rtl/] [verilog/] [Thor_divider.v] - Diff between revs 3 and 13