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[/] [thor/] [trunk/] [rtl/] [verilog/] [Thor_divider.v] - Diff between revs 13 and 42

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Rev 13 Rev 42
Line 51... Line 51...
reg [WID-1:0] aa,bb;
reg [WID-1:0] aa,bb;
reg so;
reg so;
reg [2:0] state;
reg [2:0] state;
reg [7:0] cnt;
reg [7:0] cnt;
wire cnt_done = cnt==8'd0;
wire cnt_done = cnt==8'd0;
assign done = state==DONE;
assign done = state==DONE||(state==IDLE && !ld);
assign idle = state==IDLE;
assign idle = state==IDLE;
reg ce1;
reg ce1;
reg [WID-1:0] q;
reg [WID-1:0] q;
reg [WID:0] r;
reg [WID:0] r;
wire b0 = bb <= r;
wire b0 = bb <= r;
Line 75... Line 75...
        q <= {WID{1'b0}};
        q <= {WID{1'b0}};
        r <= {WID{1'b0}};
        r <= {WID{1'b0}};
        qo <= {WID{1'b0}};
        qo <= {WID{1'b0}};
        ro <= {WID{1'b0}};
        ro <= {WID{1'b0}};
        cnt <= 8'd0;
        cnt <= 8'd0;
 
        dvByZr <= 1'b0;
        state <= IDLE;
        state <= IDLE;
end
end
else
else
begin
begin
if (abort)
if (abort)

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