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[/] [thor/] [trunk/] [rtl/] [verilog/] [Thor_execute_combo.v] - Diff between revs 10 and 13

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Rev 10 Rev 13
Line 24... Line 24...
//
//
// ============================================================================
// ============================================================================
//
//
wire [DBW-1:0] alu0_out, alu1_out;
wire [DBW-1:0] alu0_out, alu1_out;
wire alu0_done,alu1_done;
wire alu0_done,alu1_done;
 
wire alu0_idle,alu1_idle;
wire alu0_divByZero, alu1_divByZero;
wire alu0_divByZero, alu1_divByZero;
 
wire alu0_abort,alu1_abort;
 
 
Thor_alu #(.DBW(DBW),.BIG(1)) ualu0
Thor_alu #(.DBW(DBW),.BIG(1)) ualu0
(
(
    .corenum(corenum),
    .corenum(corenum),
    .rst(rst),
    .rst(rst_i),
    .clk(clk),
    .clk(clk),
    .alu_ld(alu0_ld),
    .alu_ld(alu0_ld),
 
    .alu_abort(alu0_abort),
        .alu_op(alu0_op),
        .alu_op(alu0_op),
        .alu_fn(alu0_fn),
        .alu_fn(alu0_fn),
        .alu_argA(alu0_argA),
        .alu_argA(alu0_argA),
        .alu_argB(alu0_argB),
        .alu_argB(alu0_argB),
        .alu_argC(alu0_argC),
        .alu_argC(alu0_argC),
        .alu_argI(alu0_argI),
        .alu_argI(alu0_argI),
        .alu_pc(alu0_pc),
        .alu_pc(alu0_pc),
        .insnsz(alu0_insnsz),
        .insnsz(alu0_insnsz),
        .o(alu0_out),
        .o(alu0_out),
        .alu_done(alu0_done),
        .alu_done(alu0_done),
 
        .alu_idle(alu0_idle),
        .alu_divByZero(alu0_divByZero)
        .alu_divByZero(alu0_divByZero)
);
);
 
 
Thor_alu #(.DBW(DBW),.BIG(ALU1BIG)) ualu1
Thor_alu #(.DBW(DBW),.BIG(ALU1BIG)) ualu1
(
(
    .corenum(corenum),
    .corenum(corenum),
    .rst(rst),
    .rst(rst_i),
    .clk(clk),
    .clk(clk),
    .alu_ld(alu1_ld),
    .alu_ld(alu1_ld),
 
    .alu_abort(alu1_abort),
        .alu_op(alu1_op),
        .alu_op(alu1_op),
        .alu_fn(alu1_fn),
        .alu_fn(alu1_fn),
        .alu_argA(alu1_argA),
        .alu_argA(alu1_argA),
        .alu_argB(alu1_argB),
        .alu_argB(alu1_argB),
        .alu_argC(alu1_argC),
        .alu_argC(alu1_argC),
        .alu_argI(alu1_argI),
        .alu_argI(alu1_argI),
        .alu_pc(alu1_pc),
        .alu_pc(alu1_pc),
        .insnsz(alu1_insnsz),
        .insnsz(alu1_insnsz),
        .o(alu1_out),
        .o(alu1_out),
        .alu_done(alu1_done),
        .alu_done(alu1_done),
 
        .alu_idle(alu1_idle),
    .alu_divByZero(alu1_divByZero)
    .alu_divByZero(alu1_divByZero)
);
);
 
 
function fnPredicate;
function fnPredicate;
input [3:0] pr;
input [3:0] pr;
Line 103... Line 109...
        alu1_v <= alu1_dataready;
        alu1_v <= alu1_dataready;
 
 
    alu0_id <= alu0_sourceid;
    alu0_id <= alu0_sourceid;
        alu1_id <= alu1_sourceid;
        alu1_id <= alu1_sourceid;
end
end
 
assign alu0_abort = !alu0_cmt;
 
assign alu1_abort = !alu1_cmt;
 
 
// Special flag nybble is used for INT and SYS instructions in order to turn off
// Special flag nybble is used for INT and SYS instructions in order to turn off
// segmentation while the vector jump is taking place.
// segmentation while the vector jump is taking place.
 
 
always @(alu0_op or alu0_fn or alu0_argA or alu0_argI or alu0_insnsz or alu0_pc or alu0_bt)
always @(alu0_op or alu0_fn or alu0_argA or alu0_argI or alu0_insnsz or alu0_pc or alu0_bt)
    case(alu0_op)
    case(alu0_op)
    `JSR,`JSRS,`JSRZ,`RTD,`RTE,`RTI:
    `JSR,`JSRS,`JSRZ,`RTD,`RTE,`RTI,`RTS2:
        alu0_misspc <= alu0_argA + alu0_argI;
        alu0_misspc <= alu0_argA + alu0_argI;
    `LOOP,`SYNC:
    `LOOP,`SYNC:
        alu0_misspc <= alu0_pc + alu0_insnsz;
        alu0_misspc <= alu0_pc + alu0_insnsz;
    `RTS,`RTS2:
    `RTS:
        alu0_misspc <= alu0_argA + alu0_fn[3:0];
        alu0_misspc <= alu0_argA + alu0_fn[3:0];
    `SYS,`INT:
    `SYS,`INT:
        alu0_misspc <= {4'hF,alu0_argA + {alu0_argI[DBW-5:0],4'b0}};
        alu0_misspc <= {1'b1,alu0_argA + alu0_argI};
    default:
    default:
        alu0_misspc <= (alu0_bt ? alu0_pc + alu0_insnsz : alu0_pc + alu0_insnsz + alu0_argI);
        alu0_misspc <= (alu0_bt ? alu0_pc + alu0_insnsz : alu0_pc + alu0_insnsz + alu0_argI);
    endcase
    endcase
 
 
always @(alu1_op or alu1_fn or alu1_argA or alu1_argI or alu1_insnsz or alu1_pc or alu1_bt)
always @(alu1_op or alu1_fn or alu1_argA or alu1_argI or alu1_insnsz or alu1_pc or alu1_bt)
    case(alu1_op)
    case(alu1_op)
    `JSR,`JSRS,`JSRZ,`RTD,`RTE,`RTI:
    `JSR,`JSRS,`JSRZ,`RTD,`RTE,`RTI,`RTS2:
        alu1_misspc <= alu1_argA + alu1_argI;
        alu1_misspc <= alu1_argA + alu1_argI;
    `LOOP,`SYNC:
    `LOOP,`SYNC:
        alu1_misspc <= alu1_pc + alu1_insnsz;
        alu1_misspc <= alu1_pc + alu1_insnsz;
    `RTS,`RTS2:
    `RTS:
        alu1_misspc <= alu1_argA + alu1_fn[3:0];
        alu1_misspc <= alu1_argA + alu1_fn[3:0];
    `SYS,`INT:
    `SYS,`INT:
        alu1_misspc <= {4'hF,alu1_argA + {alu1_argI[DBW-5:0],4'b0}};
        alu1_misspc <= {1'b1,alu1_argA + alu1_argI};
    default:
    default:
        alu1_misspc <= (alu1_bt ? alu1_pc + alu1_insnsz : alu1_pc + alu1_insnsz + alu1_argI);
        alu1_misspc <= (alu1_bt ? alu1_pc + alu1_insnsz : alu1_pc + alu1_insnsz + alu1_argI);
    endcase
    endcase
 
 
always @(dram0_fn or dram0_misspc or dram_bus)
always @(dram0_fn or dram0_misspc or dram_bus)
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//                      : (alu1_argB[`INSTRUCTION_S1] == `SYS_EXC)      ? alu1_argB[`INSTRUCTION_S2]
//                      : (alu1_argB[`INSTRUCTION_S1] == `SYS_EXC)      ? alu1_argB[`INSTRUCTION_S2]
//                      : `EXC_INVALID;
//                      : `EXC_INVALID;
 
 
assign alu0_branchmiss = alu0_dataready &&
assign alu0_branchmiss = alu0_dataready &&
                   ((fnIsBranch(alu0_op))  ? ((alu0_cmt && !alu0_bt) || (!alu0_cmt && alu0_bt))
                   ((fnIsBranch(alu0_op))  ? ((alu0_cmt && !alu0_bt) || (!alu0_cmt && alu0_bt))
                  : (alu0_cmtw && (alu0_op==`SYNC || alu0_op == `JSR || alu0_op == `JSRS || alu0_op == `JSRZ ||
                  : !alu0_cmt ? (alu0_op==`LOOP)
 
                  : (alu0_cmt && (alu0_op==`SYNC || alu0_op == `JSR || alu0_op == `JSRS || alu0_op == `JSRZ ||
                     alu0_op==`SYS || alu0_op==`INT ||
                     alu0_op==`SYS || alu0_op==`INT ||
                  alu0_op==`RTS || alu0_op==`RTS2 || alu0_op==`RTD || alu0_op == `RTE || alu0_op==`RTI || ((alu0_op==`LOOP) && (alu0_argA == 64'd0)))));
                  alu0_op==`RTS || alu0_op==`RTS2 || alu0_op==`RTD || alu0_op == `RTE || alu0_op==`RTI || ((alu0_op==`LOOP) && (alu0_argA == 64'd0)))));
 
 
assign alu1_branchmiss = alu1_dataready &&
assign alu1_branchmiss = alu1_dataready &&
                   ((fnIsBranch(alu1_op))  ? ((alu1_cmt && !alu1_bt) || (!alu1_cmt && alu1_bt))
                   ((fnIsBranch(alu1_op))  ? ((alu1_cmt && !alu1_bt) || (!alu1_cmt && alu1_bt))
                  : (alu1_cmtw && (alu1_op==`SYNC || alu1_op == `JSR || alu1_op == `JSRS || alu1_op == `JSRZ ||
                  : !alu1_cmt ? (alu1_op==`LOOP)
 
                  : (alu1_cmt && (alu1_op==`SYNC || alu1_op == `JSR || alu1_op == `JSRS || alu1_op == `JSRZ ||
                     alu1_op==`SYS || alu1_op==`INT ||
                     alu1_op==`SYS || alu1_op==`INT ||
                  alu1_op==`RTS || alu1_op==`RTS2 || alu1_op==`RTD || alu1_op == `RTE || alu1_op==`RTI || ((alu1_op==`LOOP) && (alu1_argA == 64'd0)))));
                  alu1_op==`RTS || alu1_op==`RTS2 || alu1_op==`RTD || alu1_op == `RTE || alu1_op==`RTI || ((alu1_op==`LOOP) && (alu1_argA == 64'd0)))));
 
 
assign  branchmiss = (alu0_branchmiss | alu1_branchmiss | mem_stringmiss | jmpi_miss),
assign  branchmiss = (alu0_branchmiss | alu1_branchmiss | mem_stringmiss | jmpi_miss),
        misspc = (jmpi_miss ? jmpi_misspc : mem_stringmiss ? dram0_misspc : alu0_branchmiss ? alu0_misspc : alu1_misspc),
        misspc = (jmpi_miss ? jmpi_misspc : mem_stringmiss ? dram0_misspc : alu0_branchmiss ? alu0_misspc : alu1_misspc),

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