| Line 24... |
Line 24... |
//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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wire [DBW-1:0] alu0_out, alu1_out;
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wire [DBW-1:0] alu0_out, alu1_out;
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wire alu0_done,alu1_done;
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wire alu0_done,alu1_done;
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wire alu0_idle,alu1_idle;
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wire alu0_divByZero, alu1_divByZero;
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wire alu0_divByZero, alu1_divByZero;
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wire alu0_abort,alu1_abort;
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Thor_alu #(.DBW(DBW),.BIG(1)) ualu0
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Thor_alu #(.DBW(DBW),.BIG(1)) ualu0
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(
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(
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.corenum(corenum),
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.corenum(corenum),
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.rst(rst),
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.rst(rst_i),
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.clk(clk),
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.clk(clk),
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.alu_ld(alu0_ld),
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.alu_ld(alu0_ld),
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.alu_abort(alu0_abort),
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.alu_op(alu0_op),
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.alu_op(alu0_op),
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.alu_fn(alu0_fn),
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.alu_fn(alu0_fn),
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.alu_argA(alu0_argA),
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.alu_argA(alu0_argA),
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.alu_argB(alu0_argB),
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.alu_argB(alu0_argB),
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.alu_argC(alu0_argC),
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.alu_argC(alu0_argC),
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.alu_argI(alu0_argI),
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.alu_argI(alu0_argI),
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.alu_pc(alu0_pc),
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.alu_pc(alu0_pc),
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.insnsz(alu0_insnsz),
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.insnsz(alu0_insnsz),
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.o(alu0_out),
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.o(alu0_out),
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.alu_done(alu0_done),
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.alu_done(alu0_done),
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.alu_idle(alu0_idle),
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.alu_divByZero(alu0_divByZero)
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.alu_divByZero(alu0_divByZero)
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);
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);
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Thor_alu #(.DBW(DBW),.BIG(ALU1BIG)) ualu1
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Thor_alu #(.DBW(DBW),.BIG(ALU1BIG)) ualu1
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(
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(
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.corenum(corenum),
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.corenum(corenum),
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.rst(rst),
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.rst(rst_i),
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.clk(clk),
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.clk(clk),
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.alu_ld(alu1_ld),
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.alu_ld(alu1_ld),
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.alu_abort(alu1_abort),
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.alu_op(alu1_op),
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.alu_op(alu1_op),
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.alu_fn(alu1_fn),
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.alu_fn(alu1_fn),
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.alu_argA(alu1_argA),
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.alu_argA(alu1_argA),
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.alu_argB(alu1_argB),
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.alu_argB(alu1_argB),
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.alu_argC(alu1_argC),
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.alu_argC(alu1_argC),
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.alu_argI(alu1_argI),
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.alu_argI(alu1_argI),
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.alu_pc(alu1_pc),
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.alu_pc(alu1_pc),
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.insnsz(alu1_insnsz),
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.insnsz(alu1_insnsz),
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.o(alu1_out),
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.o(alu1_out),
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.alu_done(alu1_done),
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.alu_done(alu1_done),
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.alu_idle(alu1_idle),
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.alu_divByZero(alu1_divByZero)
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.alu_divByZero(alu1_divByZero)
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);
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);
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function fnPredicate;
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function fnPredicate;
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input [3:0] pr;
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input [3:0] pr;
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Line 109... |
alu1_v <= alu1_dataready;
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alu1_v <= alu1_dataready;
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alu0_id <= alu0_sourceid;
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alu0_id <= alu0_sourceid;
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alu1_id <= alu1_sourceid;
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alu1_id <= alu1_sourceid;
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end
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end
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assign alu0_abort = !alu0_cmt;
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assign alu1_abort = !alu1_cmt;
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// Special flag nybble is used for INT and SYS instructions in order to turn off
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// Special flag nybble is used for INT and SYS instructions in order to turn off
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// segmentation while the vector jump is taking place.
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// segmentation while the vector jump is taking place.
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always @(alu0_op or alu0_fn or alu0_argA or alu0_argI or alu0_insnsz or alu0_pc or alu0_bt)
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always @(alu0_op or alu0_fn or alu0_argA or alu0_argI or alu0_insnsz or alu0_pc or alu0_bt)
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case(alu0_op)
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case(alu0_op)
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`JSR,`JSRS,`JSRZ,`RTD,`RTE,`RTI:
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`JSR,`JSRS,`JSRZ,`RTD,`RTE,`RTI,`RTS2:
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alu0_misspc <= alu0_argA + alu0_argI;
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alu0_misspc <= alu0_argA + alu0_argI;
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`LOOP,`SYNC:
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`LOOP,`SYNC:
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alu0_misspc <= alu0_pc + alu0_insnsz;
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alu0_misspc <= alu0_pc + alu0_insnsz;
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`RTS,`RTS2:
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`RTS:
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alu0_misspc <= alu0_argA + alu0_fn[3:0];
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alu0_misspc <= alu0_argA + alu0_fn[3:0];
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`SYS,`INT:
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`SYS,`INT:
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alu0_misspc <= {4'hF,alu0_argA + {alu0_argI[DBW-5:0],4'b0}};
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alu0_misspc <= {1'b1,alu0_argA + alu0_argI};
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default:
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default:
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alu0_misspc <= (alu0_bt ? alu0_pc + alu0_insnsz : alu0_pc + alu0_insnsz + alu0_argI);
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alu0_misspc <= (alu0_bt ? alu0_pc + alu0_insnsz : alu0_pc + alu0_insnsz + alu0_argI);
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endcase
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endcase
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always @(alu1_op or alu1_fn or alu1_argA or alu1_argI or alu1_insnsz or alu1_pc or alu1_bt)
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always @(alu1_op or alu1_fn or alu1_argA or alu1_argI or alu1_insnsz or alu1_pc or alu1_bt)
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case(alu1_op)
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case(alu1_op)
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`JSR,`JSRS,`JSRZ,`RTD,`RTE,`RTI:
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`JSR,`JSRS,`JSRZ,`RTD,`RTE,`RTI,`RTS2:
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alu1_misspc <= alu1_argA + alu1_argI;
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alu1_misspc <= alu1_argA + alu1_argI;
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`LOOP,`SYNC:
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`LOOP,`SYNC:
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alu1_misspc <= alu1_pc + alu1_insnsz;
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alu1_misspc <= alu1_pc + alu1_insnsz;
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`RTS,`RTS2:
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`RTS:
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alu1_misspc <= alu1_argA + alu1_fn[3:0];
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alu1_misspc <= alu1_argA + alu1_fn[3:0];
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`SYS,`INT:
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`SYS,`INT:
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alu1_misspc <= {4'hF,alu1_argA + {alu1_argI[DBW-5:0],4'b0}};
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alu1_misspc <= {1'b1,alu1_argA + alu1_argI};
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default:
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default:
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alu1_misspc <= (alu1_bt ? alu1_pc + alu1_insnsz : alu1_pc + alu1_insnsz + alu1_argI);
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alu1_misspc <= (alu1_bt ? alu1_pc + alu1_insnsz : alu1_pc + alu1_insnsz + alu1_argI);
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endcase
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endcase
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always @(dram0_fn or dram0_misspc or dram_bus)
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always @(dram0_fn or dram0_misspc or dram_bus)
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Line 190... |
// : (alu1_argB[`INSTRUCTION_S1] == `SYS_EXC) ? alu1_argB[`INSTRUCTION_S2]
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// : (alu1_argB[`INSTRUCTION_S1] == `SYS_EXC) ? alu1_argB[`INSTRUCTION_S2]
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// : `EXC_INVALID;
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// : `EXC_INVALID;
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assign alu0_branchmiss = alu0_dataready &&
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assign alu0_branchmiss = alu0_dataready &&
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((fnIsBranch(alu0_op)) ? ((alu0_cmt && !alu0_bt) || (!alu0_cmt && alu0_bt))
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((fnIsBranch(alu0_op)) ? ((alu0_cmt && !alu0_bt) || (!alu0_cmt && alu0_bt))
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: (alu0_cmtw && (alu0_op==`SYNC || alu0_op == `JSR || alu0_op == `JSRS || alu0_op == `JSRZ ||
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: !alu0_cmt ? (alu0_op==`LOOP)
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: (alu0_cmt && (alu0_op==`SYNC || alu0_op == `JSR || alu0_op == `JSRS || alu0_op == `JSRZ ||
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alu0_op==`SYS || alu0_op==`INT ||
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alu0_op==`SYS || alu0_op==`INT ||
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alu0_op==`RTS || alu0_op==`RTS2 || alu0_op==`RTD || alu0_op == `RTE || alu0_op==`RTI || ((alu0_op==`LOOP) && (alu0_argA == 64'd0)))));
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alu0_op==`RTS || alu0_op==`RTS2 || alu0_op==`RTD || alu0_op == `RTE || alu0_op==`RTI || ((alu0_op==`LOOP) && (alu0_argA == 64'd0)))));
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assign alu1_branchmiss = alu1_dataready &&
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assign alu1_branchmiss = alu1_dataready &&
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((fnIsBranch(alu1_op)) ? ((alu1_cmt && !alu1_bt) || (!alu1_cmt && alu1_bt))
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((fnIsBranch(alu1_op)) ? ((alu1_cmt && !alu1_bt) || (!alu1_cmt && alu1_bt))
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: (alu1_cmtw && (alu1_op==`SYNC || alu1_op == `JSR || alu1_op == `JSRS || alu1_op == `JSRZ ||
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: !alu1_cmt ? (alu1_op==`LOOP)
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: (alu1_cmt && (alu1_op==`SYNC || alu1_op == `JSR || alu1_op == `JSRS || alu1_op == `JSRZ ||
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alu1_op==`SYS || alu1_op==`INT ||
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alu1_op==`SYS || alu1_op==`INT ||
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alu1_op==`RTS || alu1_op==`RTS2 || alu1_op==`RTD || alu1_op == `RTE || alu1_op==`RTI || ((alu1_op==`LOOP) && (alu1_argA == 64'd0)))));
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alu1_op==`RTS || alu1_op==`RTS2 || alu1_op==`RTD || alu1_op == `RTE || alu1_op==`RTI || ((alu1_op==`LOOP) && (alu1_argA == 64'd0)))));
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assign branchmiss = (alu0_branchmiss | alu1_branchmiss | mem_stringmiss | jmpi_miss),
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assign branchmiss = (alu0_branchmiss | alu1_branchmiss | mem_stringmiss | jmpi_miss),
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misspc = (jmpi_miss ? jmpi_misspc : mem_stringmiss ? dram0_misspc : alu0_branchmiss ? alu0_misspc : alu1_misspc),
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misspc = (jmpi_miss ? jmpi_misspc : mem_stringmiss ? dram0_misspc : alu0_branchmiss ? alu0_misspc : alu1_misspc),
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