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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013,2015 Robert Finch, Stratford
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// \\__/ o\ (C) 2013-2016 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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alu1_id <= alu1_sourceid;
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alu1_id <= alu1_sourceid;
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end
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end
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assign alu0_abort = !alu0_cmt;
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assign alu0_abort = !alu0_cmt;
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assign alu1_abort = !alu1_cmt;
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assign alu1_abort = !alu1_cmt;
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// Special flag nybble is used for INT and SYS instructions in order to turn off
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// Special flag bit is used for INT and SYS instructions in order to turn off
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// segmentation while the vector jump is taking place.
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// segmentation while the vector jump is taking place.
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always @(alu0_op or alu0_fn or alu0_argA or alu0_argI or alu0_insnsz or alu0_pc or alu0_bt)
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always @(alu0_op or alu0_fn or alu0_argA or alu0_argI or alu0_insnsz or alu0_pc or alu0_bt)
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case(alu0_op)
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case(alu0_op)
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`JSR,`JSRS,`JSRZ,`RTD,`RTE,`RTI,`RTS2:
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`JSR,`JSRS,`JSRZ,`RTD,`RTE,`RTI,`RTS2:
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2'd1: jmpi_misspc <= {dram0_misspc[DBW-1:16],dram_bus[15:0]};
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2'd1: jmpi_misspc <= {dram0_misspc[DBW-1:16],dram_bus[15:0]};
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2'd2: jmpi_misspc <= (DBW==32) ? dram_bus[31:0] : {dram0_misspc[63:32],dram_bus[31:0]};
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2'd2: jmpi_misspc <= (DBW==32) ? dram_bus[31:0] : {dram0_misspc[63:32],dram_bus[31:0]};
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2'd3: jmpi_misspc <= dram_bus[DBW-1:0];
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2'd3: jmpi_misspc <= dram_bus[DBW-1:0];
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default: jmpi_misspc <= 32'h00000FA0; // unimplemented instruction vector
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default: jmpi_misspc <= 32'h00000FA0; // unimplemented instruction vector
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endcase
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endcase
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/*
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assign alu0_misspc = (alu0_op == `JSR || alu0_op==`JSRS || alu0_op==`JSRZ ||
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assign alu0_exc = (fnIsKMOnly(alu0_op) && !km && alu0_cmt) ? `EXC_PRIV :
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alu0_op==`RTS || alu0_op==`RTS2 || alu0_op == `RTE || alu0_op==`RTI || alu0_op==`LOOP) ? alu0_argA + alu0_argI :
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(alu0_done && alu0_divByZero && alu0_cmt) ? `EXC_DBZ :
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(alu0_op == `SYS || alu0_op==`INT) ? alu0_argA + {alu0_argI[DBW-5:0],4'b0} :
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((alu0_op==`CHKI||(alu0_op==`RR && alu0_fn==`CHK)) && !alu0_out && alu0_cmt) ? `EXC_CHK :
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(alu0_bt ? alu0_pc + alu0_insnsz : alu0_pc + alu0_insnsz + alu0_argI),
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`EXC_NONE;
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alu1_misspc = (alu1_op == `JSR || alu1_op==`JSRS || alu1_op==`JSRZ ||
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alu1_op==`RTS || alu1_op == `RTE || alu1_op==`RTI || alu1_op==`LOOP) ? alu1_argA + alu1_argI :
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assign alu1_exc = (fnIsKMOnly(alu1_op) && !km && alu1_cmt) ? `EXC_PRIV :
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(alu1_op == `SYS || alu1_op==`INT) ? alu1_argA + {alu1_argI[DBW-5:0],4'b0} :
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(alu1_done && alu1_divByZero && alu1_cmt) ? `EXC_DBZ :
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(alu1_bt ? alu1_pc + alu1_insnsz : alu1_pc + alu1_insnsz + alu1_argI);
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((alu1_op==`CHKI ||(alu1_op==`RR && alu1_fn==`CHK)) && !alu1_out && alu1_cmt) ? `EXC_CHK :
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*/
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`EXC_NONE;
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assign alu0_exc = (fnIsKMOnly(alu0_op) && !km) ? `EXC_PRIV :
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(alu0_done && alu0_divByZero) ? `EXC_DBZ : `EXC_NONE;
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// ? `EXC_NONE
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// : (alu0_argB[`INSTRUCTION_S1] == `SYS_NONE) ? `EXC_NONE
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// : (alu0_argB[`INSTRUCTION_S1] == `SYS_CALL) ? alu0_argB[`INSTRUCTION_S2]
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// : (alu0_argB[`INSTRUCTION_S1] == `SYS_MFSR) ? `EXC_NONE
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// : (alu0_argB[`INSTRUCTION_S1] == `SYS_MTSR) ? `EXC_NONE
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// : (alu0_argB[`INSTRUCTION_S1] == `SYS_RFU1) ? `EXC_INVALID
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// : (alu0_argB[`INSTRUCTION_S1] == `SYS_RFU2) ? `EXC_INVALID
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// : (alu0_argB[`INSTRUCTION_S1] == `SYS_RFU3) ? `EXC_INVALID
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// : (alu0_argB[`INSTRUCTION_S1] == `SYS_EXC) ? alu0_argB[`INSTRUCTION_S2]
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// : `EXC_INVALID;
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assign alu1_exc = (fnIsKMOnly(alu1_op) && !km) ? `EXC_PRIV :
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(alu1_done && alu1_divByZero) ? `EXC_DBZ : `EXC_NONE;
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// ? `EXC_NONE
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// : (alu1_argB[`INSTRUCTION_S1] == `SYS_NONE) ? `EXC_NONE
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// : (alu1_argB[`INSTRUCTION_S1] == `SYS_CALL) ? alu1_argB[`INSTRUCTION_S2]
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// : (alu1_argB[`INSTRUCTION_S1] == `SYS_MFSR) ? `EXC_NONE
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// : (alu1_argB[`INSTRUCTION_S1] == `SYS_MTSR) ? `EXC_NONE
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// : (alu1_argB[`INSTRUCTION_S1] == `SYS_RFU1) ? `EXC_INVALID
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// : (alu1_argB[`INSTRUCTION_S1] == `SYS_RFU2) ? `EXC_INVALID
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// : (alu1_argB[`INSTRUCTION_S1] == `SYS_RFU3) ? `EXC_INVALID
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// : (alu1_argB[`INSTRUCTION_S1] == `SYS_EXC) ? alu1_argB[`INSTRUCTION_S2]
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// : `EXC_INVALID;
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assign alu0_branchmiss = alu0_dataready &&
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assign alu0_branchmiss = alu0_dataready &&
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((fnIsBranch(alu0_op)) ? ((alu0_cmt && !alu0_bt) || (!alu0_cmt && alu0_bt))
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((fnIsBranch(alu0_op)) ? ((alu0_cmt && !alu0_bt) || (!alu0_cmt && alu0_bt))
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: !alu0_cmt ? (alu0_op==`LOOP)
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: !alu0_cmt ? (alu0_op==`LOOP)
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: (alu0_cmt && (alu0_op==`SYNC || alu0_op == `JSR || alu0_op == `JSRS || alu0_op == `JSRZ ||
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: (alu0_cmt && (alu0_op==`SYNC || alu0_op == `JSR || alu0_op == `JSRS || alu0_op == `JSRZ ||
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