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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013,2015 Robert Finch, Stratford
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// \\__/ o\ (C) 2013-2016 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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module Thor_icachemem(wclk, wce, wr, wa, wd, rclk, pc, insn);
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module Thor_icachemem(wclk, wce, wr, wa, wd, rclk, pc, insn);
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parameter DBW=64;
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parameter DBW=64;
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parameter ABW=32;
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input wclk;
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input wclk;
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input wce;
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input wce;
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input wr;
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input wr;
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input [DBW-1:0] wa;
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input [ABW-1:0] wa;
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input [DBW-1:0] wd;
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input [DBW-1:0] wd;
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input rclk;
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input rclk;
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input [DBW-1:0] pc;
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input [ABW-1:0] pc;
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output reg [127:0] insn;
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output reg [127:0] insn;
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wire [127:0] mem0a;
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wire [127:0] insn0;
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wire [127:0] mem1a;
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wire [127:0] insn1;
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reg [14:0] pcp16;
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generate
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generate
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begin : gen1
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begin : cache_mem
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if (DBW==32) begin
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if (DBW==32) begin
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syncRam2kx32_1w1r uicm0a0 (
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blk_mem_gen_0 uicm1 (
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.wclk(wclk),
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.clka(wclk), // input wire clka
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.wce(wce && wa[3:2]==2'b00),
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.ena(wce), // input wire ena
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.wr({4{wr}}),
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.wea(wr), // input wire [0 : 0] wea
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.wa(wa[14:4]),
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.addra(wa[14:2]), // input wire [14 : 0] addra
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.wd(wd),
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.dina(wd), // input wire [31 : 0] dina
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.rclk(rclk),
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.clkb(rclk), // input wire clkb
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.rce(1'b1),
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.enb(1'b1),
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.ra(pc[14:4]),
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.addrb(pc[14:4]), // input wire [12 : 0] addrb
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.o(mem0a[31:0])
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.doutb(insn0) // output wire [127 : 0] doutb
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);
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syncRam2kx32_1w1r uicm0a1 (
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.wclk(wclk),
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.wce(wce && wa[3:2]==2'b01),
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.wr({4{wr}}),
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.wa(wa[14:4]),
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.wd(wd),
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.rclk(rclk),
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.rce(1'b1),
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.ra(pc[14:4]),
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.o(mem0a[63:32])
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);
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syncRam2kx32_1w1r uicm0a2 (
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.wclk(wclk),
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.wce(wce && wa[3:2]==2'b10),
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.wr({4{wr}}),
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.wa(wa[14:4]),
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.wd(wd),
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.rclk(rclk),
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.rce(1'b1),
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.ra(pc[14:4]),
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.o(mem0a[95:64])
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);
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syncRam2kx32_1w1r uicm0a3 (
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.wclk(wclk),
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.wce(wce && wa[3:2]==2'b11),
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.wr({4{wr}}),
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.wa(wa[14:4]),
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.wd(wd),
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.rclk(rclk),
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.rce(1'b1),
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.ra(pc[14:4]),
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.o(mem0a[127:96])
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);
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);
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syncRam2kx32_1w1r uicm1a0 (
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blk_mem_gen_0 uicm2 (
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.wclk(wclk),
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.clka(wclk), // input wire clka
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.wce(wce && wa[3:2]==2'b00),
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.ena(wce), // input wire ena
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.wr({4{wr}}),
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.wea(wr), // input wire [0 : 0] wea
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.wa(wa[14:4]),
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.addra(wa[14:2]), // input wire [14 : 0] addra
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.wd(wd),
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.dina(wd), // input wire [31 : 0] dina
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.rclk(rclk),
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.clkb(rclk), // input wire clkb
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.rce(1'b1),
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.enb(1'b1),
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.ra(pcp16[14:4]),
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.addrb(pc[14:4]+11'd1), // input wire [12 : 0] addrb
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.o(mem1a[31:0])
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.doutb(insn1) // output wire [127 : 0] doutb
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);
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syncRam2kx32_1w1r uicm1a1 (
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.wclk(wclk),
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.wce(wce && wa[3:2]==2'b01),
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.wr({4{wr}}),
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.wa(wa[14:4]),
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.wd(wd),
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.rclk(rclk),
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.rce(1'b1),
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.ra(pcp16[14:4]),
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.o(mem1a[63:32])
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);
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);
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syncRam2kx32_1w1r uicm1a2 (
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end
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.wclk(wclk),
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else begin
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.wce(wce && wa[3:2]==2'b10),
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blk_mem_gen_1 uicm1 (
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.wr({4{wr}}),
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.clka(wclk), // input wire clka
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.wa(wa[14:4]),
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.ena(wce), // input wire ena
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.wd(wd),
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.wea(wr), // input wire [0 : 0] wea
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.rclk(rclk),
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.addra(wa[14:3]), // input wire [14 : 0] addra
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.rce(1'b1),
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.dina(wd), // input wire [31 : 0] dina
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.ra(pcp16[14:4]),
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.clkb(rclk), // input wire clkb
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.o(mem1a[95:64])
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.enb(1'b1),
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.addrb(pc[14:4]), // input wire [12 : 0] addrb
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.doutb(insn0) // output wire [127 : 0] doutb
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);
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);
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syncRam2kx32_1w1r uicm1a3 (
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.wclk(wclk),
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blk_mem_gen_1 uicm2 (
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.wce(wce && wa[3:2]==2'b11),
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.clka(wclk), // input wire clka
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.wr({4{wr}}),
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.ena(wce), // input wire ena
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.wa(wa[14:4]),
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.wea(wr), // input wire [0 : 0] wea
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.wd(wd),
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.addra(wa[14:3]), // input wire [14 : 0] addra
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.rclk(rclk),
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.dina(wd), // input wire [31 : 0] dina
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.rce(1'b1),
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.clkb(rclk), // input wire clkb
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.ra(pcp16[14:4]),
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.enb(1'b1),
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.o(mem1a[127:96])
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.addrb(pc[14:4]+11'd1), // input wire [12 : 0] addrb
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.doutb(insn1) // output wire [127 : 0] doutb
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);
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);
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end
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end
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end
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end
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endgenerate
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endgenerate
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always @(pc)
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pcp16 <= pc[14:0] + 15'd16;
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wire [127:0] insn0 = mem0a;
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wire [127:0] insn1 = mem1a;
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always @(pc or insn0 or insn1)
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always @(pc or insn0 or insn1)
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case(pc[3:0])
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case(pc[3:0])
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4'd0: insn <= insn0;
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4'd0: insn <= insn0;
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4'd1: insn <= {insn1[7:0],insn0[127:8]};
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4'd1: insn <= {insn1[7:0],insn0[127:8]};
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4'd2: insn <= {insn1[15:0],insn0[127:16]};
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4'd2: insn <= {insn1[15:0],insn0[127:16]};
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