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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \\__/ o\ (C) 2013,2015 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// Thor_multiplier.v
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// Thor_multiplier.v
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// - 64 bit multiplier
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// - 64 bit multiplier
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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module Thor_multiplier(rst, clk, ld, sgn, isMuli, a, b, imm, o, done);
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module Thor_multiplier(rst, clk, ld, abort, sgn, isMuli, a, b, imm, o, done, idle);
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parameter WID=64;
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parameter WID=64;
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parameter SGNADJO=3'd2;
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parameter SGNADJO=3'd2;
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parameter MULT=3'd3;
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parameter MULT=3'd3;
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parameter IDLE=3'd4;
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parameter IDLE=3'd4;
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parameter DONE=3'd5;
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parameter DONE=3'd5;
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input clk;
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input clk;
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input rst;
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input rst;
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input ld;
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input ld;
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input abort;
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input sgn;
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input sgn;
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input isMuli;
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input isMuli;
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input [WID-1:0] a;
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input [WID-1:0] a;
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input [WID-1:0] b;
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input [WID-1:0] b;
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input [WID-1:0] imm;
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input [WID-1:0] imm;
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output [WID*2-1:0] o;
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output [WID*2-1:0] o;
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reg [WID*2-1:0] o;
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reg [WID*2-1:0] o;
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output done;
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output done;
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output idle;
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reg [WID-1:0] aa,bb;
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reg [WID-1:0] aa,bb;
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reg so;
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reg so;
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reg [2:0] state;
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reg [2:0] state;
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reg [7:0] cnt;
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reg [7:0] cnt;
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wire cnt_done = cnt==8'd0;
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wire cnt_done = cnt==8'd0;
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assign done = state==DONE;
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assign done = state==DONE;
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assign idle = state==IDLE;
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reg ce1;
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reg ce1;
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reg [WID*2-1:0] prod;
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reg [WID*2-1:0] prod;
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//wire [64:0] p1 = aa[0] ? prod[127:64] + b : prod[127:64];
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//wire [64:0] p1 = aa[0] ? prod[127:64] + b : prod[127:64];
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//wire [65:0] p2 = aa[1] ? p1 + {b,1'b0} : p1;
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//wire [65:0] p2 = aa[1] ? p1 + {b,1'b0} : p1;
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wire [WID+WID/4-1:0] p1 = bb * aa[WID/4-1:0] + prod[WID*2-1:WID];
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wire [WID+WID/4-1:0] p1 = bb * aa[WID/4-1:0] + prod[WID*2-1:WID];
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o <= {WID*2{1'b0}};
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o <= {WID*2{1'b0}};
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state <= IDLE;
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state <= IDLE;
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end
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end
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else
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else
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begin
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begin
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if (!cnt_done)
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if (abort)
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cnt <= 8'd00;
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else if (!cnt_done)
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cnt <= cnt - 8'd1;
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cnt <= cnt - 8'd1;
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case(state)
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case(state)
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IDLE:
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IDLE:
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if (ld) begin
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if (ld) begin
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