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[/] [thor/] [trunk/] [rtl/] [verilog/] [Thor_multiplier.v] - Diff between revs 13 and 42

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// ============================================================================
// ============================================================================
//        __
//        __
//   \\__/ o\    (C) 2013,2015  Robert Finch, Stratford
//   \\__/ o\    (C) 2013-2016  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//       ||
//
//
// This source file is free software: you can redistribute it and/or modify 
// This source file is free software: you can redistribute it and/or modify 
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reg [WID-1:0] aa,bb;
reg [WID-1:0] aa,bb;
reg so;
reg so;
reg [2:0] state;
reg [2:0] state;
reg [7:0] cnt;
reg [7:0] cnt;
wire cnt_done = cnt==8'd0;
wire cnt_done = cnt==8'd0;
assign done = state==DONE;
assign done = state==DONE || (state==IDLE && !ld); // State == DONE
assign idle = state==IDLE;
assign idle = state==IDLE;
reg ce1;
 
reg [WID*2-1:0] prod;
reg [WID*2-1:0] prod;
//wire [64:0] p1 = aa[0] ? prod[127:64] + b : prod[127:64];
//wire [64:0] p1 = aa[0] ? prod[127:64] + b : prod[127:64];
//wire [65:0] p2 = aa[1] ? p1 + {b,1'b0} : p1;
//wire [65:0] p2 = aa[1] ? p1 + {b,1'b0} : p1;
wire [WID+WID/4-1:0] p1 = bb * aa[WID/4-1:0] + prod[WID*2-1:WID];
wire [WID+WID/4-1:0] p1 = bb * aa[WID/4-1:0] + prod[WID*2-1:WID];
 
 

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