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[/] [thor/] [trunk/] [rtl/] [verilog/] [Thor_regfile2w6r.v] - Diff between revs 3 and 42

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Rev 3 Rev 42
Line 27... Line 27...
        rclk, ra0, ra1, ra2, ra3, ra4, ra5, o0, o1, o2, o3, o4, o5);
        rclk, ra0, ra1, ra2, ra3, ra4, ra5, o0, o1, o2, o3, o4, o5);
parameter WID=64;
parameter WID=64;
input clk;
input clk;
input wr0;
input wr0;
input wr1;
input wr1;
input [5:0] wa0;
input [7:0] wa0;
input [5:0] wa1;
input [7:0] wa1;
input [WID-1:0] i0;
input [WID-1:0] i0;
input [WID-1:0] i1;
input [WID-1:0] i1;
input rclk;
input rclk;
input [5:0] ra0;
input [7:0] ra0;
input [5:0] ra1;
input [7:0] ra1;
input [5:0] ra2;
input [7:0] ra2;
input [5:0] ra3;
input [7:0] ra3;
input [5:0] ra4;
input [7:0] ra4;
input [5:0] ra5;
input [7:0] ra5;
output [WID-1:0] o0;
output [WID-1:0] o0;
output [WID-1:0] o1;
output [WID-1:0] o1;
output [WID-1:0] o2;
output [WID-1:0] o2;
output [WID-1:0] o3;
output [WID-1:0] o3;
output [WID-1:0] o4;
output [WID-1:0] o4;
output [WID-1:0] o5;
output [WID-1:0] o5;
 
 
reg [WID-1:0] regs0 [0:63];
reg [WID-1:0] regs0 [0:255];
reg [WID-1:0] regs1 [0:63];
reg [WID-1:0] regs1 [0:255];
reg [5:0] rra0,rra1,rra2,rra3,rra4,rra5;
reg [7:0] rra0,rra1,rra2,rra3,rra4,rra5;
 
 
reg whichreg [0:63];     // tracks which register file is the valid one for a given register
reg whichreg [0:255];    // tracks which register file is the valid one for a given register
 
 
// We only care about what's in the regs to begin with in simulation. In sim
// We only care about what's in the regs to begin with in simulation. In sim
// the 'x' values propagate screwing things up. In real hardware there's no such
// the 'x' values propagate screwing things up. In real hardware there's no such
// thing as an 'x'.
// thing as an 'x'.
`define SIMULATION
`define SIMULATION
Line 68... Line 68...
    end
    end
end
end
`endif
`endif
 
 
 
 
assign o0 = rra0==6'd0 ? {WID{1'b0}} :
assign o0 = rra0[5:0]==6'd0 ? {WID{1'b0}} :
        (wr1 && (rra0==wa1)) ? i1 :
        (wr1 && (rra0==wa1)) ? i1 :
        (wr0 && (rra0==wa0)) ? i0 :
        (wr0 && (rra0==wa0)) ? i0 :
        whichreg[rra0]==1'b0 ? regs0[rra0] : regs1[rra0];
        whichreg[rra0]==1'b0 ? regs0[rra0] : regs1[rra0];
assign o1 = rra1==6'd0 ? {WID{1'b0}} :
assign o1 = rra1[5:0]==6'd0 ? {WID{1'b0}} :
        (wr1 && (rra1==wa1)) ? i1 :
        (wr1 && (rra1==wa1)) ? i1 :
        (wr0 && (rra1==wa0)) ? i0 :
        (wr0 && (rra1==wa0)) ? i0 :
        whichreg[rra1]==1'b0 ? regs0[rra1] : regs1[rra1];
        whichreg[rra1]==1'b0 ? regs0[rra1] : regs1[rra1];
assign o2 = rra2==6'd0 ? {WID{1'b0}} :
assign o2 = rra2[5:0]==6'd0 ? {WID{1'b0}} :
        (wr1 && (rra2==wa1)) ? i1 :
        (wr1 && (rra2==wa1)) ? i1 :
        (wr0 && (rra2==wa0)) ? i0 :
        (wr0 && (rra2==wa0)) ? i0 :
        whichreg[rra2]==1'b0 ? regs0[rra2] : regs1[rra2];
        whichreg[rra2]==1'b0 ? regs0[rra2] : regs1[rra2];
assign o3 = rra3==6'd0 ? {WID{1'b0}} :
assign o3 = rra3[5:0]==6'd0 ? {WID{1'b0}} :
        (wr1 && (rra3==wa1)) ? i1 :
        (wr1 && (rra3==wa1)) ? i1 :
        (wr0 && (rra3==wa0)) ? i0 :
        (wr0 && (rra3==wa0)) ? i0 :
        whichreg[rra3]==1'b0 ? regs0[rra3] : regs1[rra3];
        whichreg[rra3]==1'b0 ? regs0[rra3] : regs1[rra3];
assign o4 = rra4==6'd0 ? {WID{1'b0}} :
assign o4 = rra4[5:0]==6'd0 ? {WID{1'b0}} :
    (wr1 && (rra4==wa1)) ? i1 :
    (wr1 && (rra4==wa1)) ? i1 :
    (wr0 && (rra4==wa0)) ? i0 :
    (wr0 && (rra4==wa0)) ? i0 :
    whichreg[rra4]==1'b0 ? regs0[rra4] : regs1[rra4];
    whichreg[rra4]==1'b0 ? regs0[rra4] : regs1[rra4];
assign o5 = rra5==6'd0 ? {WID{1'b0}} :
assign o5 = rra5[5:0]==6'd0 ? {WID{1'b0}} :
    (wr1 && (rra5==wa1)) ? i1 :
    (wr1 && (rra5==wa1)) ? i1 :
    (wr0 && (rra5==wa0)) ? i0 :
    (wr0 && (rra5==wa0)) ? i0 :
    whichreg[rra5]==1'b0 ? regs0[rra5] : regs1[rra5];
    whichreg[rra5]==1'b0 ? regs0[rra5] : regs1[rra5];
 
 
always @(posedge clk)
always @(posedge clk)

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