| Line 27... |
Line 27... |
rclk, ra0, ra1, ra2, ra3, ra4, ra5, o0, o1, o2, o3, o4, o5);
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rclk, ra0, ra1, ra2, ra3, ra4, ra5, o0, o1, o2, o3, o4, o5);
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parameter WID=64;
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parameter WID=64;
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input clk;
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input clk;
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input wr0;
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input wr0;
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input wr1;
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input wr1;
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input [5:0] wa0;
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input [7:0] wa0;
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input [5:0] wa1;
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input [7:0] wa1;
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input [WID-1:0] i0;
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input [WID-1:0] i0;
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input [WID-1:0] i1;
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input [WID-1:0] i1;
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input rclk;
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input rclk;
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input [5:0] ra0;
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input [7:0] ra0;
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input [5:0] ra1;
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input [7:0] ra1;
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input [5:0] ra2;
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input [7:0] ra2;
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input [5:0] ra3;
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input [7:0] ra3;
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input [5:0] ra4;
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input [7:0] ra4;
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input [5:0] ra5;
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input [7:0] ra5;
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output [WID-1:0] o0;
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output [WID-1:0] o0;
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output [WID-1:0] o1;
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output [WID-1:0] o1;
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output [WID-1:0] o2;
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output [WID-1:0] o2;
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output [WID-1:0] o3;
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output [WID-1:0] o3;
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output [WID-1:0] o4;
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output [WID-1:0] o4;
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output [WID-1:0] o5;
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output [WID-1:0] o5;
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reg [WID-1:0] regs0 [0:63];
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reg [WID-1:0] regs0 [0:255];
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reg [WID-1:0] regs1 [0:63];
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reg [WID-1:0] regs1 [0:255];
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reg [5:0] rra0,rra1,rra2,rra3,rra4,rra5;
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reg [7:0] rra0,rra1,rra2,rra3,rra4,rra5;
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reg whichreg [0:63]; // tracks which register file is the valid one for a given register
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reg whichreg [0:255]; // tracks which register file is the valid one for a given register
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// We only care about what's in the regs to begin with in simulation. In sim
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// We only care about what's in the regs to begin with in simulation. In sim
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// the 'x' values propagate screwing things up. In real hardware there's no such
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// the 'x' values propagate screwing things up. In real hardware there's no such
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// thing as an 'x'.
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// thing as an 'x'.
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`define SIMULATION
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`define SIMULATION
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| Line 68... |
Line 68... |
end
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end
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end
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end
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`endif
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`endif
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assign o0 = rra0==6'd0 ? {WID{1'b0}} :
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assign o0 = rra0[5:0]==6'd0 ? {WID{1'b0}} :
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(wr1 && (rra0==wa1)) ? i1 :
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(wr1 && (rra0==wa1)) ? i1 :
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(wr0 && (rra0==wa0)) ? i0 :
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(wr0 && (rra0==wa0)) ? i0 :
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whichreg[rra0]==1'b0 ? regs0[rra0] : regs1[rra0];
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whichreg[rra0]==1'b0 ? regs0[rra0] : regs1[rra0];
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assign o1 = rra1==6'd0 ? {WID{1'b0}} :
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assign o1 = rra1[5:0]==6'd0 ? {WID{1'b0}} :
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(wr1 && (rra1==wa1)) ? i1 :
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(wr1 && (rra1==wa1)) ? i1 :
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(wr0 && (rra1==wa0)) ? i0 :
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(wr0 && (rra1==wa0)) ? i0 :
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whichreg[rra1]==1'b0 ? regs0[rra1] : regs1[rra1];
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whichreg[rra1]==1'b0 ? regs0[rra1] : regs1[rra1];
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assign o2 = rra2==6'd0 ? {WID{1'b0}} :
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assign o2 = rra2[5:0]==6'd0 ? {WID{1'b0}} :
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(wr1 && (rra2==wa1)) ? i1 :
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(wr1 && (rra2==wa1)) ? i1 :
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(wr0 && (rra2==wa0)) ? i0 :
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(wr0 && (rra2==wa0)) ? i0 :
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whichreg[rra2]==1'b0 ? regs0[rra2] : regs1[rra2];
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whichreg[rra2]==1'b0 ? regs0[rra2] : regs1[rra2];
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assign o3 = rra3==6'd0 ? {WID{1'b0}} :
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assign o3 = rra3[5:0]==6'd0 ? {WID{1'b0}} :
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(wr1 && (rra3==wa1)) ? i1 :
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(wr1 && (rra3==wa1)) ? i1 :
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(wr0 && (rra3==wa0)) ? i0 :
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(wr0 && (rra3==wa0)) ? i0 :
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whichreg[rra3]==1'b0 ? regs0[rra3] : regs1[rra3];
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whichreg[rra3]==1'b0 ? regs0[rra3] : regs1[rra3];
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assign o4 = rra4==6'd0 ? {WID{1'b0}} :
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assign o4 = rra4[5:0]==6'd0 ? {WID{1'b0}} :
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(wr1 && (rra4==wa1)) ? i1 :
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(wr1 && (rra4==wa1)) ? i1 :
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(wr0 && (rra4==wa0)) ? i0 :
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(wr0 && (rra4==wa0)) ? i0 :
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whichreg[rra4]==1'b0 ? regs0[rra4] : regs1[rra4];
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whichreg[rra4]==1'b0 ? regs0[rra4] : regs1[rra4];
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assign o5 = rra5==6'd0 ? {WID{1'b0}} :
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assign o5 = rra5[5:0]==6'd0 ? {WID{1'b0}} :
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(wr1 && (rra5==wa1)) ? i1 :
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(wr1 && (rra5==wa1)) ? i1 :
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(wr0 && (rra5==wa0)) ? i0 :
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(wr0 && (rra5==wa0)) ? i0 :
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whichreg[rra5]==1'b0 ? regs0[rra5] : regs1[rra5];
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whichreg[rra5]==1'b0 ? regs0[rra5] : regs1[rra5];
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always @(posedge clk)
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always @(posedge clk)
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