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URL https://opencores.org/ocsvn/thor/thor/trunk

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[/] [thor/] [trunk/] [software/] [boot_tb/] [boot.asm] - Diff between revs 16 and 28

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Line 20... Line 20...
; You should have received a copy of the GNU General Public License
; You should have received a copy of the GNU General Public License
; along with this program.  If not, see .
; along with this program.  If not, see .
;
;
; ============================================================================
; ============================================================================
;
;
 
.include "C:\Cores4\Thor\trunk\software\FMTK\source\kernel\FMTK_Equates.inc"
 
 
SCRSZ   EQU     2604
SCRSZ   EQU     2604
 
_BS             EQU     0x07
CR      EQU     0x0D            ;ASCII equates
CR      EQU     0x0D            ;ASCII equates
LF      EQU     0x0A
LF      EQU     0x0A
TAB     EQU     0x09
TAB     EQU     0x09
CTRLC   EQU     0x03
CTRLC   EQU     0x03
BS              EQU     0x07
 
CTRLH   EQU     0x08
CTRLH   EQU     0x08
CTRLI   EQU     0x09
CTRLI   EQU     0x09
CTRLJ   EQU     0x0A
CTRLJ   EQU     0x0A
CTRLK   EQU     0x0B
CTRLK   EQU     0x0B
CTRLM   EQU 0x0D
CTRLM   EQU 0x0D
Line 38... Line 39...
CTRLX   EQU     0x18
CTRLX   EQU     0x18
XON             EQU     0x11
XON             EQU     0x11
XOFF    EQU     0x13
XOFF    EQU     0x13
ESC             EQU     0x1B
ESC             EQU     0x1B
 
 
 
SC_TAB          EQU             $0D
SC_LSHIFT       EQU             $12
SC_LSHIFT       EQU             $12
SC_RSHIFT       EQU             $59
SC_RSHIFT       EQU             $59
SC_KEYUP        EQU             $F0
SC_KEYUP        EQU             $F0
SC_EXTEND       EQU             $E0
SC_EXTEND       EQU             $E0
SC_CTRL         EQU             $14
SC_CTRL         EQU             $14
Line 81... Line 83...
                org             $0000
                org             $0000
                dw              0                                ; the first word is unused
                dw              0                                ; the first word is unused
Milliseconds    dw              0
Milliseconds    dw              0
m_w                             dh              0
m_w                             dh              0
m_z                             dh              0
m_z                             dh              0
 
FMTK_SchedulerIRQ_vec   dw      0
 
Running_                dw              0
 
IOFocusNdx_             dw              0
 
iof_switch_             db              0
 
                align   8
 
NextRdy_                dw              0
 
PrevRdy_                dw              0
 
 
KeyState1               db              0
KeyState1               db              0
KeyState2               db              0
KeyState2               db              0
KeybdLEDs               db              0
KeybdLEDs               db              0
KeybdWaitFlag   db              0
KeybdWaitFlag   db              0
 
                align   2
 
KeybdHead               db              0
 
KeybdTail               db              0
 
KeybdBufSz              db              0
 
KeybdBuf                fill.b  128,0
 
                align   2
CursorX                 dc              0
CursorX                 dc              0
CursorY                 dc              0
CursorY                 dc              0
VideoPos                dc              0
VideoPos                dc              0
                align   4
                align   4
NormAttr                dh              0
NormAttr                dh              0
Line 169... Line 184...
                ; setup break vector
                ; setup break vector
                lla             r1,cs:brk_jmp
                lla             r1,cs:brk_jmp
                ldi             r2,#0
                ldi             r2,#0
                bsr             set_vector
                bsr             set_vector
 
 
 
                ; setup system scheduler vector
 
                ; points to an RTE at startup
 
                lla             r1,cs:tms_jmp
 
                ldi             r2,#2
 
                bsr             set_vector
 
                lla             r1,cs:rte_jmp
 
                ldi             r2,#3
 
                bsr             set_vector
 
 
                ; setup Video BIOS vector
                ; setup Video BIOS vector
                lla             r1,cs:vb_jmp
                lla             r1,cs:vb_jmp
                ldi             r2,#10
                ldi             r2,#10
                bsr             set_vector
                bsr             set_vector
 
 
Line 198... Line 222...
                sh              r0,Milliseconds
                sh              r0,Milliseconds
                lla             r1,cs:msi_jmp
                lla             r1,cs:msi_jmp
                ldi             r2,#193
                ldi             r2,#193
                bsr             set_vector
                bsr             set_vector
 
 
                ; setup IRQ vector
 
                lla             r1,cs:tms_jmp
 
                ldi             r2,#194
 
                bsr             set_vector
 
 
 
                ; setup BTNU vector
                ; setup BTNU vector
                lla             r1,cs:btnu_jmp
                lla             r1,cs:btnu_jmp
                ldi             r2,#200
                ldi             r2,#200
                bsr             set_vector
                bsr             set_vector
 
 
Line 218... Line 237...
                ; setup data bus error vector
                ; setup data bus error vector
                lla             r1,cs:dbe_jmp
                lla             r1,cs:dbe_jmp
                ldi             r2,#251
                ldi             r2,#251
                bsr             set_vector
                bsr             set_vector
 
 
 
                ldi             r1,#JCB_Array
 
                sw              r1,zs:RunningJCB_
 
                sw              r1,zs:IOFocusNdx_       ; set I/O focus to BIOS
 
                ldi             r1,#TCB_Array
 
                sw              r1,zs:RunningTCB_
 
                sb              r0,zs:iof_switch_       ; reset switch flag
 
                mov             tr,r0
 
                bsr             KeybdInit
 
 
 
                jsr             FMTKInitialize_
 
 
                ; Initialize PIC
                ; Initialize PIC
                ldi             r1,#%00000111           ; time slice interrupt is edge sensitive
                ldi             r1,#%00000111           ; nmi, time slice interrupt is edge sensitive
                sh              r1,hs:PIC_ES
                sh              r1,hs:PIC_ES
                ldi             r1,#%100000111          ; enable time slice interrupt, msi, nmi
                ldi             r1,#%000001111          ; enable time slice interrupt, msi, nmi
                sh              r1,hs:PIC_IE
                sh              r1,hs:PIC_IE
 
 
                ; Initialize random number generator
                ; Initialize random number generator
                ; m_z and m_w must not be zero
                ; m_z and m_w must not be zero
                ldi             r1,#$88888888
                ldi             r1,#$88888888
Line 350... Line 380...
                bsr             MonGetch1                       ; get character skipping spaces
                bsr             MonGetch1                       ; get character skipping spaces
                cmpi    p0,r1,#'$'                      ; skip over prompt
                cmpi    p0,r1,#'$'                      ; skip over prompt
p0.eq   br              .0001
p0.eq   br              .0001
                cmpi    p0,r1,#'d'                      ; debug ?
                cmpi    p0,r1,#'d'                      ; debug ?
p0.eq   bsr             Debugger
p0.eq   bsr             Debugger
 
p0.eq   br              .prompt
                cmpi    p0,r1,#'g'
                cmpi    p0,r1,#'g'
p0.eq   bsr             GoGraphics
p0.eq   bsr             GoGraphics
 
p0.eq   br              .prompt
                cmpi    p0,r1,#'t'
                cmpi    p0,r1,#'t'
p0.eq   bsr             MonGetch
p0.eq   bsr             MonGetch
p0.eq   cmpi    p0,r1,#'x'
p0.eq   cmpi    p0,r1,#'x'
p0.eq   bsr             GoText
p0.eq   bsr             GoText
 
p0.eq   br              .prompt
                cmpi    p0,r1,'r'
                cmpi    p0,r1,'r'
p0.eq   bsr             RandomDots
p0.eq   bsr             RandomDots
 
p0.eq   br              .prompt
                cmpi    p0,r1,#'c'
                cmpi    p0,r1,#'c'
p0.eq   bsr             VBClearScreen
p0.eq   bsr             VBClearScreen
p0.eq   mov             r1,r0
p0.eq   mov             r1,r0
p0.eq   mov             r2,r0
p0.eq   mov             r2,r0
p0.eq   ldi             r6,#2
p0.eq   ldi             r6,#2
Line 408... Line 442...
                lws             c1,[r31]
                lws             c1,[r31]
                addui   r31,r31,#8
                addui   r31,r31,#8
                rts
                rts
 
 
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
 
; Go into graphics mode, four lines of text at bottom.
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
 
 
GoGraphics:
GoGraphics:
                lhu             r3,Vidregs
                lhu             r3,Vidregs
                ldi             r1,#4
                ldi             r1,#4
                sc              r1,Textrows
                sc              r1,Textrows
                sh              r1,hs:4[r3]             ; # rows
                sh              r1,hs:4[r3]             ; # rows
                ldi             r1,#720
                ldi             r1,#240
                sh              r1,hs:12[r3]    ; window top
                sh              r1,hs:12[r3]    ; window top
 
                mov             r1,r0                   ; reset cursor position
 
                mov             r2,r0
 
                ldi             r6,#2
 
                sys             #10
                rts
                rts
 
 
 
;------------------------------------------------------------------------------
 
; Go back to full text mode.
 
;------------------------------------------------------------------------------
 
 
GoText:
GoText:
                lhu             r3,Vidregs
                lhu             r3,Vidregs
                ldi             r1,#31
                ldi             r1,#31
                sc              r1,Textrows
                sc              r1,Textrows
                sh              r1,hs:4[r3]             ; # rows
                sh              r1,hs:4[r3]             ; # rows
                ldi             r1,#17
                ldi             r1,#17
                sh              r1,hs:12[r3]    ; window top
                sh              r1,hs:12[r3]    ; window top
 
                mov             r1,r0                   ; reset cursor position
 
                mov             r2,r0
 
                ldi             r6,#2
 
                sys             #10
                rts
                rts
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Uses George Marsaglia's multiply method
// Uses George Marsaglia's multiply method
//
//
Line 470... Line 517...
// Display random dots on the graphics screen.
// Display random dots on the graphics screen.
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
RandomDots:
RandomDots:
                addui   r31,r31,#-8
                addui   r31,r31,#-8
                sws             c1,[r31]
                sws             c1,[r31]                ; stack the return address
                mov             r4,r0
                mov             r4,r0
.0001:
.0001:
                bsr             gen_rand                ; get random bitmap memory location
                bsr             gen_rand                ; get random bitmap memory location
                modu    r2,r1,#172032   ; mod the memory size
                modui   r2,r1,#172032   ; mod the memory size
                shli    r2,r2,#1                ; *2 for 16 bit data
                _2addui r2,r2,#$FFA00000        ; *2 for 16 bit data, generate address
                bsr             gen_rand                ; get random color
                bsr             gen_rand                ; get random color
                modui   r3,r1,#$1000    ; limit to 12 bits
                modui   r3,r1,#$1000    ; limit to 12 bits
                sc              r3,zs:$FFA00000[r2]     ; store color in memory
                sc              r3,zs:[r2]              ; store color in memory
                addui   r4,r4,#1                ; increment loop index
                addui   r4,r4,#1                ; increment loop index
                andi    r4,r4,#$FFF             ;
                andi    r4,r4,#$FFF             ;
                tst             p0,r4                   ; check if time to check for keypress
                tst             p1,r4                   ; check if time to check for keypress
p0.eq   bsr             KeybdGetCharNoWait      ; try get a key, but don't wait
p1.ne   br              .0001
                tst             p0,r1                   ; branch if no key pressed
                bsr             KeybdGetCharNoWait      ; try get a key, but don't wait
p0.lt   br              RandomDots.0001
                tst             p1,r1                   ; branch if no key pressed
                lws             c1,[r31]
p1.lt   br              RandomDots.0001
 
                lws             c1,[r31]                ; restore return address
                addui   r31,r31,#8
                addui   r31,r31,#8
                rts
                rts
 
 
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
 
 
Line 563... Line 611...
 
 
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
; Save the register context.
; Save the register context.
;
;
; Parameters:
; Parameters:
;       DS points to app's data space
;       tr points to app's TCB
;
;
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
 
 
save_context:
save_context:
                sw              r1,reg_save+8*1
                sw              r1,TCB_r1[tr]
                sw              r2,reg_save+8*2
                sw              r2,TCB_r2[tr]
                sw              r3,reg_save+8*3
                sw              r3,TCB_r3[tr]
                sw              r4,reg_save+8*4
                sw              r4,TCB_r4[tr]
                sw              r5,reg_save+8*5
                sw              r5,TCB_r5[tr]
                sw              r6,reg_save+8*6
                sw              r6,TCB_r6[tr]
                sw              r7,reg_save+8*7
                sw              r7,TCB_r7[tr]
                sw              r8,reg_save+8*8
                sw              r8,TCB_r8[tr]
                sw              r9,reg_save+8*9
                sw              r9,TCB_r9[tr]
                sw              r10,reg_save+8*10
                sw              r10,TCB_r10[tr]
                sw              r11,reg_save+8*11
                sw              r11,TCB_r11[tr]
                sw              r12,reg_save+8*12
                sw              r12,TCB_r12[tr]
                sw              r13,reg_save+8*13
                sw              r13,TCB_r13[tr]
                sw              r14,reg_save+8*14
                sw              r14,TCB_r14[tr]
                sw              r15,reg_save+8*15
                sw              r15,TCB_r15[tr]
                sw              r16,reg_save+8*16
                sw              r16,TCB_r16[tr]
                sw              r17,reg_save+8*17
                sw              r17,TCB_r17[tr]
                sw              r18,reg_save+8*18
                sw              r18,TCB_r18[tr]
                sw              r19,reg_save+8*19
                sw              r19,TCB_r19[tr]
                sw              r20,reg_save+8*20
                sw              r20,TCB_r20[tr]
                sw              r21,reg_save+8*21
                sw              r21,TCB_r21[tr]
                sw              r22,reg_save+8*22
                sw              r22,TCB_r22[tr]
                sw              r23,reg_save+8*23
                sw              r23,TCB_r23[tr]
                sw              r24,reg_save+8*24
                sw              r24,TCB_r24[tr]
                sw              r25,reg_save+8*25
                sw              r25,TCB_r25[tr]
                sw              r26,reg_save+8*26
                sw              r26,TCB_r26[tr]
                sw              r27,reg_save+8*27
                sw              r27,TCB_r27[tr]
                sw              r28,reg_save+8*28
                sws             ds,TCB_ds[tr]
                sw              r29,reg_save+8*29
                sws             es,TCB_es[tr]
                sw              r30,reg_save+8*30
                sws             fs,TCB_fs[tr]
                sw              r31,reg_save+8*31
                sws             gs,TCB_gs[tr]
                sws             ds,sreg_save+8*1
                sws             hs,TCB_hs[tr]
                sws             es,sreg_save+8*2
                sws             ss,TCB_ss[tr]
                sws             fs,sreg_save+8*3
                sws             cs,TCB_cs[tr]
                sws             gs,sreg_save+8*4
                sws             ds.lmt,TCB_dslmt[tr]
                sws             hs,sreg_save+8*5
                sws             es.lmt,TCB_eslmt[tr]
                sws             ss,sreg_save+8*6
                sws             fs.lmt,TCB_fslmt[tr]
                sws             cs,sreg_save+8*7
                sws             gs.lmt,TCB_gslmt[tr]
                sws             ds.lmt,sreg_save+8*9
                sws             hs.lmt,TCB_hslmt[tr]
                sws             es.lmt,sreg_save+8*10
                sws             ss.lmt,TCB_sslmt[tr]
                sws             fs.lmt,sreg_save+8*11
                sws             cs.lmt,TCB_cslmt[tr]
                sws             gs.lmt,sreg_save+8*12
                sws             c1,TCB_c1[tr]
                sws             hs.lmt,sreg_save+8*13
                sws             c2,TCB_c2[tr]
                sws             ss.lmt,sreg_save+8*14
                sws             c3,TCB_c3[tr]
                sws             cs.lmt,sreg_save+8*15
                sws             c4,TCB_c4[tr]
                sws             c1,creg_save+8*1
                sws             c5,TCB_c5[tr]
                sws             c2,creg_save+8*2
                sws             c6,TCB_c6[tr]
                sws             c3,creg_save+8*3
                sws             c7,TCB_c7[tr]
                sws             c4,creg_save+8*4
                sws             c8,TCB_c8[tr]
                sws             c5,creg_save+8*5
                sws             c9,TCB_c9[tr]
                sws             c6,creg_save+8*6
                sws             c10,TCB_c10[tr]
                sws             c7,creg_save+8*7
                sws             c11,TCB_c11[tr]
                sws             c8,creg_save+8*8
;               sws             c13,TCB_c13[tr]
                sws             c9,creg_save+8*9
;               sws             c14,TCB_c14[tr]
                sws             c10,creg_save+8*10
                sws             pregs,TCB_pregs[tr]
                sws             c11,creg_save+8*11
 
                sws             c13,creg_save+8*13
 
                sws             c14,creg_save+8*14
 
                sws             pregs,preg_save
 
                rte
                rte
 
 
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
; Restore register context.
; Restore register context.
; Parameters:
; Parameters:
;       DS points to app's data space.
;       DS points to app's data space.
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
 
 
restore_context:
restore_context:
                lw              r1,reg_save+8*1
                lw              r1,TCB_r1[tr]
                lw              r2,reg_save+8*2
                lw              r2,TCB_r2[tr]
                lw              r3,reg_save+8*3
                lw              r3,TCB_r3[tr]
                lw              r4,reg_save+8*4
                lw              r4,TCB_r4[tr]
                lw              r5,reg_save+8*5
                lw              r5,TCB_r5[tr]
                lw              r6,reg_save+8*6
                lw              r6,TCB_r6[tr]
                lw              r7,reg_save+8*7
                lw              r7,TCB_r7[tr]
                lw              r8,reg_save+8*8
                lw              r8,TCB_r8[tr]
                lw              r9,reg_save+8*9
                lw              r9,TCB_r9[tr]
                lw              r10,reg_save+8*10
                lw              r10,TCB_r10[tr]
                lw              r11,reg_save+8*11
                lw              r11,TCB_r11[tr]
                lw              r12,reg_save+8*12
                lw              r12,TCB_r12[tr]
                lw              r13,reg_save+8*13
                lw              r13,TCB_r13[tr]
                lw              r14,reg_save+8*14
                lw              r14,TCB_r14[tr]
                lw              r15,reg_save+8*15
                lw              r15,TCB_r15[tr]
                lw              r16,reg_save+8*16
                lw              r16,TCB_r16[tr]
                lw              r17,reg_save+8*17
                lw              r17,TCB_r17[tr]
                lw              r18,reg_save+8*18
                lw              r18,TCB_r18[tr]
                lw              r19,reg_save+8*19
                lw              r19,TCB_r19[tr]
                lw              r20,reg_save+8*20
                lw              r20,TCB_r20[tr]
                lw              r21,reg_save+8*21
                lw              r21,TCB_r21[tr]
                lw              r22,reg_save+8*22
                lw              r22,TCB_r22[tr]
                lw              r23,reg_save+8*23
                lw              r23,TCB_r23[tr]
                lw              r24,reg_save+8*24
                lw              r24,TCB_r24[tr]
                lw              r25,reg_save+8*25
                lw              r25,TCB_r25[tr]
                lw              r26,reg_save+8*26
                lw              r26,TCB_r26[tr]
                lw              r27,reg_save+8*27
                lw              r27,TCB_r27[tr]
                lw              r28,reg_save+8*28
                lws             ds,TCB_ds[tr]
                lw              r29,reg_save+8*29
                lws             es,TCB_es[tr]
                lw              r30,reg_save+8*30
                lws             fs,TCB_fs[tr]
                lw              r31,reg_save+8*31
                lws             gs,TCB_gs[tr]
;               lws             ds,sreg_save+8*1
                lws             hs,TCB_hs[tr]
                lws             es,sreg_save+8*2
                lws             ss,TCB_ss[tr]
                lws             fs,sreg_save+8*3
                lws             cs,TCB_cs[tr]
                lws             gs,sreg_save+8*4
                lws             ds.lmt,TCB_dslmt[tr]
                lws             hs,sreg_save+8*5
                lws             es.lmt,TCB_eslmt[tr]
                lws             ss,sreg_save+8*6
                lws             fs.lmt,TCB_fslmt[tr]
                lws             cs,sreg_save+8*7
                lws             gs.lmt,TCB_gslmt[tr]
;               lws             ds.lmt,sreg_save+8*9
                lws             hs.lmt,TCB_hslmt[tr]
                lws             es.lmt,sreg_save+8*10
                lws             ss.lmt,TCB_sslmt[tr]
                lws             fs.lmt,sreg_save+8*11
                lws             cs.lmt,TCB_cslmt[tr]
                lws             gs.lmt,sreg_save+8*12
                lws             c1,TCB_c1[tr]
                lws             hs.lmt,sreg_save+8*13
                lws             c2,TCB_c2[tr]
                lws             ss.lmt,sreg_save+8*14
                lws             c3,TCB_c3[tr]
                lws             cs.lmt,sreg_save+8*15
                lws             c4,TCB_c4[tr]
                lws             c1,creg_save+8*1
                lws             c5,TCB_c5[tr]
                lws             c2,creg_save+8*2
                lws             c6,TCB_c6[tr]
                lws             c3,creg_save+8*3
                lws             c7,TCB_c7[tr]
                lws             c4,creg_save+8*4
                lws             c8,TCB_c8[tr]
                lws             c5,creg_save+8*5
                lws             c9,TCB_c9[tr]
                lws             c6,creg_save+8*6
                lws             c10,TCB_c10[tr]
                lws             c7,creg_save+8*7
                lws             c11,TCB_c11[tr]
                lws             c8,creg_save+8*8
;               lws             c13,TCB_c13[tr]
                lws             c9,creg_save+8*9
;               lws             c14,TCB_c14[tr]
                lws             c10,creg_save+8*10
                lws             pregs,TCB_pregs[tr]
                lws             c11,creg_save+8*11
 
;               lws             c13,creg_save+8*13
 
                lws             c14,creg_save+8*14
 
                lws             pregs,preg_save
 
                rte
                rte
 
 
 
.include "c:\cores4\thor\trunk\software\FMTK\source\kernel\FMTKc.s"
.include "video.asm"
.include "video.asm"
.include "keyboard.asm"
 
.include "serial.asm"
.include "serial.asm"
 
.include "keyboard.asm"
.include "debugger.asm"
.include "debugger.asm"
 
 
 
 
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
; BTNU IRQ routine.
; BTNU IRQ routine.
;
;
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;
;
btnu_rout:
btnu_rout:
                sync
                sync
                addui   r31,r31,#-16
                addui   r31,r31,#-24
                sw              r1,[r31]
                sw              r1,[r31]
                sws             hs,8[r31]
                sws             hs,8[r31]
 
                sws             hs.lmt,16[r31]
 
 
                ; set I/O segment
                ; set I/O segment
                ldis    hs,#$FFD00000
                ldis    hs,#$FFD00000
 
                ldis    hs.lmt,#$100000
 
 
                ; update on-screen IRQ live indicator
                ; update on-screen IRQ live indicator
                lh              r1,hs:TEXTSCR+312
                inc.h   hs:TEXTSCR+312
                addui   r1,r1,#1
 
                sh              r1,hs:TEXTSCR+312
 
 
 
                ; restore regs and return
                ; restore regs and return
                lw              r1,[r31]
                lw              r1,[r31]
                lws             hs,8[r31]
                lws             hs,8[r31]
                addui   r31,r31,#16
                lws             hs.lmt,16[r31]
 
                addui   r31,r31,#24
                sync
                sync
                rti
                rti
 
 
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
 
 
spur_rout:
spur_rout:
                sync
                sync
                ldi             r31,#INT_STACK-16
                addui   r31,r31,#-24
                sw              r1,[r31]
                sw              r1,[r31]
                sws             hs,8[r31]
                sws             hs,8[r31]
 
                sws             hs.lmt,16[r31]
 
 
                ; set I/O segment
                ; set I/O segment
                ldis    hs,#$FFD00000
                ldis    hs,#$FFD00000
 
                ldis    hs.lmt,#$100000
 
 
;               ldi             r1,#18
;               ldi             r1,#18
;               sc              r1,hs:LEDS
;               sc              r1,hs:LEDS
 
 
                ; update on-screen IRQ live indicator
                ; update on-screen IRQ live indicator
                lh              r1,hs:TEXTSCR+316
                inc.h   hs:TEXTSCR+316
                addui   r1,r1,#1
 
                sh              r1,hs:TEXTSCR+316
 
 
 
                ; restore regs and return
                ; restore regs and return
                lw              r1,[r31]
                lw              r1,[r31]
                lws             hs,8[r31]
                lws             hs,8[r31]
 
                lws             hs.lmt,16[r31]
 
                addui   r31,r31,#24
                sync
                sync
                rti
                rti
 
 
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
; Uninitialized interrupt
; Uninitialized interrupt
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
uii_rout:
uii_rout:
                sync
                sync
                ldi             r31,#INT_STACK-16
                addui   r31,r31,#-24
                sw              r1,[r31]
                sw              r1,[r31]
                sws             hs,8[r31]
                sws             hs,8[r31]
 
                sws             hs.lmt,16[r31]
 
 
                ; set I/O segment
                ; set I/O segment
                ldis    hs,#$FFD00000
                ldis    hs,#$FFD00000
 
                ldis    hs.lmt,#$100000
 
 
                ; update on-screen IRQ live indicator
                ; update on-screen IRQ live indicator
                ldi             r1,#'U'|%011000000_111111111_00_00000000
                ldi             r1,#'U'|%011000000_111111111_00_00000000
                sh              r1,hs:TEXTSCR+320
                sh              r1,hs:TEXTSCR+320
 
 
Line 802... Line 848...
uii_hang:
uii_hang:
                br              uii_hang
                br              uii_hang
                ; restore regs and return
                ; restore regs and return
                lw              r1,[r31]
                lw              r1,[r31]
                lws             hs,8[r31]
                lws             hs,8[r31]
 
                lws             hs.lmt,16[r31]
 
                addui   r31,r31,#24
                sync
                sync
                rti
                rti
 
 
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
; Non-maskable interrupt routine.
; Non-maskable interrupt routine.
;
;
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;
;
nmi_rout:
nmi_rout:
                sync
                sync
                ldi             r31,#INT_STACK-16
                addui   r31,r31,#-24
                sw              r1,[r31]
                sw              r1,[r31]
                sws             hs,8[r31]
                sws             hs,8[r31]
 
                sws             hs.lmt,16[r31]
 
 
                ; set I/O segment
                ; set I/O segment
                ldis    hs,#$FFD00000
                ldis    hs,#$FFD00000
 
                ldis    hs.lmt,#$100000
 
 
                ldi             r1,#16
                ldi             r1,#16
                sc              r1,hs:LEDS
                sc              r1,hs:LEDS
 
 
                ; reset the edge sense circuit to re-enable interrupts
                ; reset the edge sense circuit to re-enable interrupts
Line 834... Line 884...
                sh              r1,hs:TEXTSCR+324
                sh              r1,hs:TEXTSCR+324
 
 
                ; restore regs and return
                ; restore regs and return
                lw              r1,[r31]
                lw              r1,[r31]
                lws             hs,8[r31]
                lws             hs,8[r31]
 
                lws             hs.lmt,16[r31]
 
                addui   r31,r31,#24
                sync
                sync
                rti
                rti
 
 
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
; Millisecond (1024 Hz) interrupt routine.
; Millisecond (1024 Hz) interrupt routine.
;
;
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;
;
msi_rout:
msi_rout:
                sync
                sync
                addui   r31,r31,#-16
                addui   sp,sp,#-32
                sw              r1,[r31]
                sw              r1,[sp]
                sws             hs,8[r31]
                sws             hs,8[sp]
 
                sws             hs.lmt,16[sp]
 
                sws             c1,24[sp]
 
 
                ; set I/O segment
                ; set I/O segment
                ldis    hs,#$FFD00000
                ldis    hs,#$FFD00000
 
                ldis    hs.lmt,#$100000
 
 
                ldi             r1,#24
                ldi             r1,#24
                sc              r1,hs:LEDS
                sc              r1,hs:LEDS
 
 
                ; reset the edge sense circuit to re-enable interrupts
                ; reset the edge sense circuit to re-enable interrupts
                ldi             r1,#1
                ldi             r1,#1
                sh              r1,hs:PIC_ESR
                sh              r1,hs:PIC_ESR
 
 
                ; update milliseconds
                ; update milliseconds
                lh              r1,zs:Milliseconds
                lw              r1,zs:Milliseconds
                addui   r1,r1,#1
                addui   r1,r1,#1
                sh              r1,zs:Milliseconds
                sw              r1,zs:Milliseconds
 
 
                ; restore regs and return
                ; restore regs and return
                lw              r1,[r31]
                lw              r1,[sp]
                lws             hs,8[r31]
                lws             hs,8[sp]
                addui   r31,r31,#16
                lws             hs.lmt,16[sp]
 
                lws             c1,24[sp]
 
                addui   sp,sp,#32
                sync
                sync
                rti
                rti
 
 
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
; Time Slice IRQ routine.
; Time Slice IRQ routine.
;
;
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;
;
tms_rout:
tms_rout:
                sync
                sync
                addui   r31,r31,#-16
                addui   r31,r31,#-24
                sw              r1,[r31]
                sw              r1,[r31]
                sws             hs,8[r31]
                sws             hs,8[r31]
 
                sws             hs.lmt,16[r31]
 
 
                ; set I/O segment
                ; set I/O segment
                ldis    hs,#$FFD00000
                ldis    hs,#$FFD00000
 
                ldis    hs.lmt,#$100000
 
 
                ldi             r1,#32
                ldi             r1,#32
                sc              r1,hs:LEDS
                sc              r1,hs:LEDS
 
 
                ; reset the edge sense circuit to re-enable interrupts
                ; reset the edge sense circuit to re-enable interrupts
                ldi             r1,#2
                ldi             r1,#2
                sh              r1,hs:PIC_ESR
                sh              r1,hs:PIC_ESR
 
 
                ; update on-screen IRQ live indicator
                ; update on-screen IRQ live indicator
                lh              r1,hs:TEXTSCR+328
                inc.h   hs:TEXTSCR+328
                addui   r1,r1,#1
 
                sh              r1,hs:TEXTSCR+328
 
 
 
                ; restore regs and return
                ; restore regs and return
                lw              r1,[r31]
                lw              r1,[r31]
                lws             hs,8[r31]
                lws             hs,8[r31]
                addui   r31,r31,#16
                lws             hs.lmt,16[r31]
 
                addui   r31,r31,#24
                sync
                sync
                rti
                rte
 
 
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
; Data bus error routine.
; Data bus error routine.
;
;
;
;
Line 1020... Line 1078...
                jmp             uii_rout[c0]
                jmp             uii_rout[c0]
                align   8
                align   8
vb_jmp:
vb_jmp:
                jmp             VideoBIOSCall[c0]
                jmp             VideoBIOSCall[c0]
                align   8
                align   8
ser_jmp:
 
                jmp             SerialIRQ[c0]
 
                align   8
 
dbe_jmp:
dbe_jmp:
                jmp             dbe_rout[c0]
                jmp             dbe_rout[c0]
                align   8
                align   8
svc_jmp:
svc_jmp:
                jmp             save_context[c0]
                jmp             save_context[c0]
Line 1041... Line 1096...
                jmp             btnu_rout[c0]
                jmp             btnu_rout[c0]
                align   8
                align   8
rti_jmp:
rti_jmp:
km_jmp:
km_jmp:
                rti
                rti
 
                align   8
 
rte_jmp:
 
                rte
 
 
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
; Reset Point
; Reset Point
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
 
 

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