URL https://opencores.org/ocsvn/thor/thor/trunk

Subversion Repositories thor

[/] [thor/] [trunk/] [software/] [emuThor/] [source/] [clsPIC.cpp] - Diff between revs 30 and 32

Rev 30	Rev 32
Line 17...	Line 17...
`irq30Hz = false;`	`irq30Hz = false;`
`irq1024Hz = false;`	`irq1024Hz = false;`
`irqKeyboard = false;`	`irqKeyboard = false;`
`}`	`}`

`No newline at end of file`	`No newline at end of file`
	`unsigned int clsPIC::Read(unsigned int ad) {`
	`int nn;`
	`unsigned int dat;`
	`switch((ad >> 3) & 7) {`
	`case 0:`
	`return vecno;`
	`default:`
	`dat = 0;`
	`for (nn = 0; nn < 16; nn++)`
	`dat \|= (enables[nn] << nn);`
	`return dat;`
	`}`
	`}`

	`void clsPIC::Write(unsigned int ad, unsigned int dat, unsigned int mask) {`
	`int nn;`
	`switch((ad >> 3) & 7) {`
	`case 1:`
	`for (nn = 0; nn < 16; nn++)`
	`enables[nn] = (dat & (1 << nn)) != 0;`
	`break;`
	`case 2:`
	`enables[dat & 15] = false;`
	`break;`
	`case 3:`
	`enables[dat & 15] = true;`
	`break;`
	`case 5:`
	`if (dat==1)`
	`irq1024Hz = false;`
	`if (dat==2)`
	`irq30Hz = false;`
	`if (dat==7)`
	`irqUart = false;`
	`if (dat==3)`
	`irqKeyboard = false;`
	`break;`
	`}`
	`}`

	`void clsPIC::Step(void) {`
	`vecno = 192;`
	`irq = system1.cpu2.irq = false;`
	`if (enables[7] & irqUart) {`
	`irq = system1.cpu2.irq = true;`
	`vecno = 192+7;`
	`}`
	`if (enables[3] & irqKeyboard) {`
	`irq = system1.cpu2.irq = true;`
	`vecno = 192+3;`
	`}`
	`if (enables[2] & irq30Hz) {`
	`irq = system1.cpu2.irq = true;`
	`vecno = 192+2;`
	`}`
	`if (enables[1] & irq1024Hz) {`
	`irq = system1.cpu2.irq = true;`
	`vecno = 192+1;`
	`}`
	`system1.cpu2.vecno = vecno;`
	`}`



`No newline at end of file`	`No newline at end of file`