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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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package TinyXconfig is
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constant XLEN : integer := 32;
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subtype cpuWord is std_logic_vector(XLEN -1 downto 0);
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constant ccModeLeft : integer := XLEN - 1;
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constant ccModeRight : integer := XLEN - 4;
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constant aluModeLeft : integer := XLEN - 5;
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constant aluModeRight : integer := XLEN - 8;
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constant memmuxBit : integer := XLEN - 9;
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constant dstClkLeft : integer := XLEN - 10;
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constant dstClkRight : integer := XLEN - 12;
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constant writeCycleBit : integer := XLEN - 13;
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constant opamuxLeft : integer := XLEN - 14;
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constant opamuxRight : integer := XLEN - 16;
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constant valmuxBit : integer := XLEN - 17;
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constant opbmuxLeft : integer := XLEN - 18;
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constant opbmuxRight : integer := XLEN - 20;
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constant flagUpdateBit : integer := XLEN - 21;
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constant carryUseBit : integer := XLEN - 22;
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-- two bits unused
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constant immediateLeft : integer := XLEN - 25;
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function getStdLogicVectorZeroes(int : in integer) return std_logic_vector;
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end TinyXconfig;
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package body TinyXconfig is
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function getStdLogicVectorZeroes(int : in integer) return std_logic_vector is
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variable result : std_logic_vector(int -1 downto 0);
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begin
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for index in result'range loop
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result(index) := '0';
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end loop;
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return result;
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end getStdLogicVectorZeroes;
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end TinyXconfig;
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