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[/] [tiny64/] [trunk/] [mux2.vhd] - Diff between revs 2 and 4
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use work.TinyXconfig.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity mux2 is
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Port ( ina : in cpuWord;
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inb : in cpuWord;
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mout : out cpuWord;
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sel : in std_logic);
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end mux2;
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architecture Behavioral of mux2 is
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begin
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mx2: for i in ina'range generate
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mout(i) <= (ina(i) and (not sel)) or (inb(i) and sel);
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end generate;
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end Behavioral;
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