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[/] [tiny_aes/] [trunk/] [rtl/] [aes_128.v] - Diff between revs 4 and 6

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module aes_128(clk, state, key, out);
module aes_128(clk, state, key, out);
    input          clk;
    input          clk;
    input  [127:0] state, key;
    input  [127:0] state, key;
    output [127:0] out;
    output [127:0] out;
    reg    [127:0] s0, k0;
    reg    [127:0] s0, k0;
    wire   [127:0] s1, k1, s2, k2, s3, k3, s4, k4, s5, k5,
    wire   [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9,
                   s6, k6, s7, k7, s8, k8, s9, k9, s10;
                   k1, k2, k3, k4, k5, k6, k7, k8, k9,
 
                   k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b;
 
 
    always @ (posedge clk)
    always @ (posedge clk)
      begin
      begin
        s0 <= state ^ key;
        s0 <= state ^ key;
        k0 <= key;
        k0 <= key;
      end
      end
    assign out = s10;
 
    one_round_128
 
        r1 (clk, s0, k0, s1, k1, 8'h1),
 
        r2 (clk, s1, k1, s2, k2, 8'h2),
 
        r3 (clk, s2, k2, s3, k3, 8'h4),
 
        r4 (clk, s3, k3, s4, k4, 8'h8),
 
        r5 (clk, s4, k4, s5, k5, 8'h10),
 
        r6 (clk, s5, k5, s6, k6, 8'h20),
 
        r7 (clk, s6, k6, s7, k7, 8'h40),
 
        r8 (clk, s7, k7, s8, k8, 8'h80),
 
        r9 (clk, s8, k8, s9, k9, 8'h1b);
 
    final_round_128
 
        rf (clk, s9, k9, s10, 8'h36);
 
endmodule
 
 
 
module one_round_128(clk, state_in, key_in, state_out, key_out, rcon);
    expand_key_128
    input              clk;
        a1 (clk, k0, k1, k0b, 8'h1),
    input      [127:0] state_in,  key_in;
        a2 (clk, k1, k2, k1b, 8'h2),
    input      [7:0]   rcon;
        a3 (clk, k2, k3, k2b, 8'h4),
    output reg [127:0] state_out, key_out;
        a4 (clk, k3, k4, k3b, 8'h8),
    wire [31:0] s0,  s1,  s2,  s3,
        a5 (clk, k4, k5, k4b, 8'h10),
                v0,  v1,  v2,  v3,
        a6 (clk, k5, k6, k5b, 8'h20),
                z0,  z1,  z2,  z3,
        a7 (clk, k6, k7, k6b, 8'h40),
                p00, p01, p02, p03,
        a8 (clk, k7, k8, k7b, 8'h80),
                p10, p11, p12, p13,
        a9 (clk, k8, k9, k8b, 8'h1b),
                p20, p21, p22, p23,
       a10 (clk, k9,   , k9b, 8'h36);
                p30, p31, p32, p33,
 
                k0,  k1,  k2,  k3;
    one_round
    reg  [31:0] k0a, k1a, k2a, k3a;
        r1 (clk, s0, k0b, s1),
    wire [31:0] k0b, k1b, k2b, k3b, k4a;
        r2 (clk, s1, k1b, s2),
 
        r3 (clk, s2, k2b, s3),
 
        r4 (clk, s3, k3b, s4),
 
        r5 (clk, s4, k4b, s5),
 
        r6 (clk, s5, k5b, s6),
 
        r7 (clk, s6, k6b, s7),
 
        r8 (clk, s7, k7b, s8),
 
        r9 (clk, s8, k8b, s9);
 
 
    assign {k0, k1, k2, k3} = key_in;
    final_round
    assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
        rf (clk, s9, k9b, out);
    assign v1 = v0 ^ k1;
 
    assign v2 = v1 ^ k2;
 
    assign v3 = v2 ^ k3;
 
    always @ (posedge clk)
 
        {k0a, k1a, k2a, k3a} <= {v0, v1, v2, v3};
 
    S4
 
        S4_0 (clk, {k3[23:0], k3[31:24]}, k4a);
 
    assign k0b = k0a ^ k4a;
 
    assign k1b = k1a ^ k4a;
 
    assign k2b = k2a ^ k4a;
 
    assign k3b = k3a ^ k4a;
 
    always @ (posedge clk)
 
        key_out <= {k0b, k1b, k2b, k3b};
 
 
 
    assign {s0, s1, s2, s3} = state_in;
 
    table_lookup
 
        t0 (clk, s0, p00, p01, p02, p03),
 
        t1 (clk, s1, p10, p11, p12, p13),
 
        t2 (clk, s2, p20, p21, p22, p23),
 
        t3 (clk, s3, p30, p31, p32, p33);
 
    assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0b;
 
    assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1b;
 
    assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2b;
 
    assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3b;
 
    always @ (posedge clk)
 
        state_out <= {z0, z1, z2, z3};
 
endmodule
endmodule
 
 
module final_round_128(clk, state_in, key_in, state_out, rcon);
module expand_key_128(clk, in, out_1, out_2, rcon);
    input              clk;
    input              clk;
    input      [127:0] state_in,  key_in;
    input      [127:0] in;
    input      [7:0]   rcon;
    input      [7:0]   rcon;
    output reg [127:0] state_out;
    output reg [127:0] out_1;
    wire [31:0] s0,  s1,  s2,  s3,
    output     [127:0] out_2;
                v0,  v1,  v2,  v3,
    wire       [31:0]  k0, k1, k2, k3,
                z0,  z1,  z2,  z3,
                       v0, v1, v2, v3;
                k0,  k1,  k2,  k3;
 
    reg  [31:0] k0a, k1a, k2a, k3a;
    reg  [31:0] k0a, k1a, k2a, k3a;
    wire [31:0] k0b, k1b, k2b, k3b, k4a;
    wire [31:0] k0b, k1b, k2b, k3b, k4a;
    wire [7:0]  p00, p01, p02, p03,
 
                p10, p11, p12, p13,
 
                p20, p21, p22, p23,
 
                p30, p31, p32, p33;
 
 
 
    assign {k0, k1, k2, k3} = key_in;
    assign {k0, k1, k2, k3} = in;
 
 
    assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
    assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
    assign v1 = v0 ^ k1;
    assign v1 = v0 ^ k1;
    assign v2 = v1 ^ k2;
    assign v2 = v1 ^ k2;
    assign v3 = v2 ^ k3;
    assign v3 = v2 ^ k3;
 
 
    always @ (posedge clk)
    always @ (posedge clk)
        {k0a, k1a, k2a, k3a} <= {v0, v1, v2, v3};
        {k0a, k1a, k2a, k3a} <= {v0, v1, v2, v3};
 
 
    S4
    S4
        S4_0 (clk, {k3[23:0], k3[31:24]}, k4a);
        S4_0 (clk, {k3[23:0], k3[31:24]}, k4a);
 
 
    assign k0b = k0a ^ k4a;
    assign k0b = k0a ^ k4a;
    assign k1b = k1a ^ k4a;
    assign k1b = k1a ^ k4a;
    assign k2b = k2a ^ k4a;
    assign k2b = k2a ^ k4a;
    assign k3b = k3a ^ k4a;
    assign k3b = k3a ^ k4a;
 
 
    assign {s0, s1, s2, s3} = state_in;
 
    S4
 
        S4_1 (clk, s0, {p00, p01, p02, p03}),
 
        S4_2 (clk, s1, {p10, p11, p12, p13}),
 
        S4_3 (clk, s2, {p20, p21, p22, p23}),
 
        S4_4 (clk, s3, {p30, p31, p32, p33});
 
    assign z0 = {p00, p11, p22, p33} ^ k0b;
 
    assign z1 = {p10, p21, p32, p03} ^ k1b;
 
    assign z2 = {p20, p31, p02, p13} ^ k2b;
 
    assign z3 = {p30, p01, p12, p23} ^ k3b;
 
    always @ (posedge clk)
    always @ (posedge clk)
        state_out <= {z0, z1, z2, z3};
        out_1 <= {k0b, k1b, k2b, k3b};
 
 
 
    assign out_2 = {k0b, k1b, k2b, k3b};
endmodule
endmodule
 
 
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