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module aes_128(clk, state, key, out);
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module aes_128(clk, state, key, out);
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input clk;
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input clk;
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input [127:0] state, key;
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input [127:0] state, key;
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output [127:0] out;
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output [127:0] out;
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reg [127:0] s0, k0;
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reg [127:0] s0, k0;
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wire [127:0] s1, k1, s2, k2, s3, k3, s4, k4, s5, k5,
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wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9,
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s6, k6, s7, k7, s8, k8, s9, k9, s10;
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k1, k2, k3, k4, k5, k6, k7, k8, k9,
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k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b;
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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s0 <= state ^ key;
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s0 <= state ^ key;
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k0 <= key;
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k0 <= key;
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end
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end
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assign out = s10;
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one_round_128
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r1 (clk, s0, k0, s1, k1, 8'h1),
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r2 (clk, s1, k1, s2, k2, 8'h2),
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r3 (clk, s2, k2, s3, k3, 8'h4),
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r4 (clk, s3, k3, s4, k4, 8'h8),
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r5 (clk, s4, k4, s5, k5, 8'h10),
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r6 (clk, s5, k5, s6, k6, 8'h20),
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r7 (clk, s6, k6, s7, k7, 8'h40),
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r8 (clk, s7, k7, s8, k8, 8'h80),
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r9 (clk, s8, k8, s9, k9, 8'h1b);
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final_round_128
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rf (clk, s9, k9, s10, 8'h36);
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endmodule
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module one_round_128(clk, state_in, key_in, state_out, key_out, rcon);
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expand_key_128
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input clk;
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a1 (clk, k0, k1, k0b, 8'h1),
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input [127:0] state_in, key_in;
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a2 (clk, k1, k2, k1b, 8'h2),
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input [7:0] rcon;
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a3 (clk, k2, k3, k2b, 8'h4),
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output reg [127:0] state_out, key_out;
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a4 (clk, k3, k4, k3b, 8'h8),
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wire [31:0] s0, s1, s2, s3,
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a5 (clk, k4, k5, k4b, 8'h10),
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v0, v1, v2, v3,
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a6 (clk, k5, k6, k5b, 8'h20),
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z0, z1, z2, z3,
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a7 (clk, k6, k7, k6b, 8'h40),
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p00, p01, p02, p03,
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a8 (clk, k7, k8, k7b, 8'h80),
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p10, p11, p12, p13,
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a9 (clk, k8, k9, k8b, 8'h1b),
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p20, p21, p22, p23,
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a10 (clk, k9, , k9b, 8'h36);
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p30, p31, p32, p33,
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k0, k1, k2, k3;
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one_round
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reg [31:0] k0a, k1a, k2a, k3a;
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r1 (clk, s0, k0b, s1),
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wire [31:0] k0b, k1b, k2b, k3b, k4a;
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r2 (clk, s1, k1b, s2),
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r3 (clk, s2, k2b, s3),
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r4 (clk, s3, k3b, s4),
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r5 (clk, s4, k4b, s5),
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r6 (clk, s5, k5b, s6),
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r7 (clk, s6, k6b, s7),
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r8 (clk, s7, k7b, s8),
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r9 (clk, s8, k8b, s9);
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assign {k0, k1, k2, k3} = key_in;
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final_round
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assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
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rf (clk, s9, k9b, out);
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assign v1 = v0 ^ k1;
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assign v2 = v1 ^ k2;
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assign v3 = v2 ^ k3;
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always @ (posedge clk)
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{k0a, k1a, k2a, k3a} <= {v0, v1, v2, v3};
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S4
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S4_0 (clk, {k3[23:0], k3[31:24]}, k4a);
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assign k0b = k0a ^ k4a;
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assign k1b = k1a ^ k4a;
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assign k2b = k2a ^ k4a;
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assign k3b = k3a ^ k4a;
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always @ (posedge clk)
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key_out <= {k0b, k1b, k2b, k3b};
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assign {s0, s1, s2, s3} = state_in;
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table_lookup
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t0 (clk, s0, p00, p01, p02, p03),
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t1 (clk, s1, p10, p11, p12, p13),
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t2 (clk, s2, p20, p21, p22, p23),
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t3 (clk, s3, p30, p31, p32, p33);
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assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0b;
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assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1b;
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assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2b;
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assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3b;
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always @ (posedge clk)
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state_out <= {z0, z1, z2, z3};
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endmodule
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endmodule
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module final_round_128(clk, state_in, key_in, state_out, rcon);
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module expand_key_128(clk, in, out_1, out_2, rcon);
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input clk;
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input clk;
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input [127:0] state_in, key_in;
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input [127:0] in;
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input [7:0] rcon;
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input [7:0] rcon;
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output reg [127:0] state_out;
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output reg [127:0] out_1;
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wire [31:0] s0, s1, s2, s3,
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output [127:0] out_2;
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v0, v1, v2, v3,
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wire [31:0] k0, k1, k2, k3,
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z0, z1, z2, z3,
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v0, v1, v2, v3;
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k0, k1, k2, k3;
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reg [31:0] k0a, k1a, k2a, k3a;
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reg [31:0] k0a, k1a, k2a, k3a;
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wire [31:0] k0b, k1b, k2b, k3b, k4a;
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wire [31:0] k0b, k1b, k2b, k3b, k4a;
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wire [7:0] p00, p01, p02, p03,
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p10, p11, p12, p13,
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p20, p21, p22, p23,
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p30, p31, p32, p33;
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assign {k0, k1, k2, k3} = key_in;
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assign {k0, k1, k2, k3} = in;
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assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
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assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
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assign v1 = v0 ^ k1;
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assign v1 = v0 ^ k1;
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assign v2 = v1 ^ k2;
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assign v2 = v1 ^ k2;
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assign v3 = v2 ^ k3;
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assign v3 = v2 ^ k3;
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always @ (posedge clk)
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always @ (posedge clk)
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{k0a, k1a, k2a, k3a} <= {v0, v1, v2, v3};
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{k0a, k1a, k2a, k3a} <= {v0, v1, v2, v3};
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S4
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S4
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S4_0 (clk, {k3[23:0], k3[31:24]}, k4a);
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S4_0 (clk, {k3[23:0], k3[31:24]}, k4a);
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assign k0b = k0a ^ k4a;
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assign k0b = k0a ^ k4a;
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assign k1b = k1a ^ k4a;
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assign k1b = k1a ^ k4a;
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assign k2b = k2a ^ k4a;
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assign k2b = k2a ^ k4a;
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assign k3b = k3a ^ k4a;
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assign k3b = k3a ^ k4a;
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assign {s0, s1, s2, s3} = state_in;
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S4
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S4_1 (clk, s0, {p00, p01, p02, p03}),
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S4_2 (clk, s1, {p10, p11, p12, p13}),
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S4_3 (clk, s2, {p20, p21, p22, p23}),
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S4_4 (clk, s3, {p30, p31, p32, p33});
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assign z0 = {p00, p11, p22, p33} ^ k0b;
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assign z1 = {p10, p21, p32, p03} ^ k1b;
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assign z2 = {p20, p31, p02, p13} ^ k2b;
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assign z3 = {p30, p01, p12, p23} ^ k3b;
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always @ (posedge clk)
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always @ (posedge clk)
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state_out <= {z0, z1, z2, z3};
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out_1 <= {k0b, k1b, k2b, k3b};
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assign out_2 = {k0b, k1b, k2b, k3b};
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endmodule
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endmodule
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