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Line 4... |
2. 16-bit address bus
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2. 16-bit address bus
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3. fixed 16-bit instruction length
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3. fixed 16-bit instruction length
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4. use a small amount of "rich" instructions to do powerful things
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4. use a small amount of "rich" instructions to do powerful things
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5. 1 instruction per clock cycle
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5. 1 instruction per clock cycle
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Relative moves:
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In order to provide uesfulness to the segment-carryover feature, there are a few options for moving a "relative" amount to a register, including IP and SP
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A relative move differs in most of the opcodes in that the relative factor is treated as a signed value.
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so for instance, a
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mov r0,50
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mov_relative r0, -10
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in the ned, r0 will end up being 40. Although this feature won't see much use in general registers, IP and SP are special because of the option of using the
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segment-carryover feature. This means that SP and IP, while being 8-bit registers, can function very similar to a 16-bit register, enabling full usage of the available address space.
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Register list:
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Register list:
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r0-r5 general purpose registers
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r0-r5 general purpose registers
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sp stack pointer (represented as r6)
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sp stack pointer (represented as r6)
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ip instruction pointer register (represented as r7)
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ip instruction pointer register (represented as r7)
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cs, ds, es, ss segment registers (code segment, data segment, extra segment, stack segment)
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cs, ds, es, ss segment registers (code segment, data segment, extra segment, stack segment)
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| Line 21... |
Line 31... |
last 1 bit: conditional
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last 1 bit: conditional
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second byte:
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second byte:
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first 1 bit: second portion of condition (if not immediate) (1 for only if false)
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first 1 bit: second portion of condition (if not immediate) (1 for only if false)
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next 1 bit: use extra segment
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next 1 bit: use extra segment
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next 3 bits: other register
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next 3 bits: other register. If not 3rd register, top bit specifies which register bank, others unused
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last 3 bits: extra opcode information or third register. such as for ADD it could be target=source+third_register
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last 3 bits: extra opcode information or third register. such as for ADD it could be target=source+third_register
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...or second byte is immediate value
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...or second byte is immediate value
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For opcodes requiring 3 registers but without room, the target opcode is assume to be the second operation. Such as for AND, target=source AND target
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For opcodes requiring 3 registers but without room, the target opcode is assume to be the second operation. Such as for AND, target=source AND target
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| Line 34... |
Line 44... |
immediates:
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immediates:
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1. move reg, immediate
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1. move reg, immediate
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2. move [reg], immediate
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2. move [reg], immediate
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3. push and move reg, immediate (or call immediate)
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3. push and move reg, immediate (or call immediate)
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4. push immediate
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4. push immediate
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5. jmp immediate
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5. mov (relative) immediate
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groups: (limited to 2 registers and no immediates. each group has 8 opcodes)
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groups: (limited to 2 registers and no immediates. each group has 8 opcodes)
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group 1:
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group 1:
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move(store) [reg],reg
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move(store) [reg],reg
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move(load) reg,[reg]
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move(load) reg,[reg]
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| Line 87... |
Line 98... |
push extended segmentreg, reg (equivalent to push seg; push reg)
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push extended segmentreg, reg (equivalent to push seg; push reg)
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pop extended segmentreg, reg (equivalent to pop reg; pop seg)
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pop extended segmentreg, reg (equivalent to pop reg; pop seg)
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reset processor (will completely reset the processor to starting state, but not RAM or anything else)
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reset processor (will completely reset the processor to starting state, but not RAM or anything else)
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group 6:
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group 6:
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set register bank 0
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set default register bank to 0 (can be condensed to 1 opcode)
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set register bank 1
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set default register bank to 1
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push extended reg, reg
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push extended reg, reg
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pop extended reg,reg
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pop extended reg,reg
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enable carryover seg
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disable CS carryover seg
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mov relative reg, reg
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exchange reg, reg
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3 register instructions:
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3 register instructions:
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1. add reg1, reg2, reg3 (reg1=reg2+reg3)
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1. add reg1, reg2, reg3 (reg1=reg2+reg3)
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2. sub reg1, reg2, reg3
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2. sub reg1, reg2, reg3
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| Line 141... |
Line 155... |
DS is used in all "normal" memory references
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DS is used in all "normal" memory references
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SS is used in all push and pop instructions
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SS is used in all push and pop instructions
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ES is used when the ExtraSegment bit is set for either push/pop or normal memory references
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ES is used when the ExtraSegment bit is set for either push/pop or normal memory references
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CS is only used for fetching instructions
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CS is only used for fetching instructions
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Segment carryover:
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In order to overcome the limitations of only having a 256 byte segment, there is a workaround option to "pretend" that IP is a 16 bit register.
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When CS carryover is enabled, when IP rollover from 255 to 0 or whatever, CS will be incremented. This makes it so that if you start at address 0:0.
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you can continue as far as needed into the address space without having to do ugly far jumps at each of the borders.
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States needed:
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States needed:
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0. reset
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0. reset
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1. decode current instruction (All without memory capable within 1 clock cycle)
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1. decode current instruction (All without memory capable within 1 clock cycle)
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2. increment IP(and SP if needed) and fetch next instruction
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2. increment IP(and SP if needed) and fetch next instruction
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