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Line 44... |
immediates:
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immediates:
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1. move reg, immediate
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1. move reg, immediate
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2. move [reg], immediate
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2. move [reg], immediate
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3. push and move reg, immediate (or call immediate)
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3. push and move reg, immediate (or call immediate)
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4. push immediate
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4. push immediate
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5. mov (relative) immediate
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5. move (relative) reg, immediate
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groups: (limited to 2 registers and no immediates. each group has 8 opcodes)
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groups: (limited to 2 registers and no immediates. each group has 8 opcodes)
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group 1:
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group 1:
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move(store) [reg],reg
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move(store) [reg],reg
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| Line 103... |
Line 103... |
set default register bank to 0 (can be condensed to 1 opcode)
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set default register bank to 0 (can be condensed to 1 opcode)
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set default register bank to 1
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set default register bank to 1
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push extended reg, reg
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push extended reg, reg
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pop extended reg,reg
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pop extended reg,reg
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enable carryover seg
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enable carryover seg
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disable CS carryover seg
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disable carryover seg
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mov relative reg, reg
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mov relative reg, reg
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exchange reg, reg
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exchange reg, reg
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3 register instructions:
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3 register instructions:
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1. add reg1, reg2, reg3 (reg1=reg2+reg3)
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1. add reg1, reg2, reg3 (reg1=reg2+reg3)
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2. sub reg1, reg2, reg3
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2. sub reg1, reg2, reg3
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opcodes used: 12 of 16. 4 more opcodes available. Decide what to do with the room later.
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opcodes used: 13 of 16. 3 more opcodes available. Decide what to do with the room later.
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Possible canidates for opcode compression include
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* Push immediate (room for 3 sub-opcodes)
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* push and pop reg (room for 7 sub-opcodes each)
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* equals 0 and not equals 0 (room for 7 sub-opcodes each)
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* Set TR and Reset TR (room for 64 opcodes each)
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* increment and decrement reg (room for 7 opcodes each)
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* enable and disable carry over (room for 7 opcodes each)
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* set register bank 0 and 1 (room for 64 opcodes each)
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0 -nop (doesn't do a thing)
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0 -nop (doesn't do a thing)
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1 -move immediate (only uses first byte)
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1 -move immediate (only uses first byte)
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2 -move
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2 -move
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| Line 159... |
Line 167... |
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Segment carryover:
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Segment carryover:
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In order to overcome the limitations of only having a 256 byte segment, there is a workaround option to "pretend" that IP is a 16 bit register.
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In order to overcome the limitations of only having a 256 byte segment, there is a workaround option to "pretend" that IP is a 16 bit register.
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When CS carryover is enabled, when IP rollover from 255 to 0 or whatever, CS will be incremented. This makes it so that if you start at address 0:0.
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When CS carryover is enabled, when IP rollover from 255 to 0 or whatever, CS will be incremented. This makes it so that if you start at address 0:0.
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you can continue as far as needed into the address space without having to do ugly far jumps at each of the borders.
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you can continue as far as needed into the address space without having to do ugly far jumps at each of the borders.
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Carryover can only be done on CS and SS. The required circuitry is not implemented for DS or ES due to an extreme level of complexity required for it, also
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it would only lead to unncessarily complex code
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Also of note is that `move relative` implements a "carryover" component. This component will work on either IP or SP, and uses CS and SS respectively.
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If used on other registers, there will be no carry over functionality, though it can be used as an easy way to add or subtract an immediate from a register.
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States needed:
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States needed:
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0. reset
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0. reset
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1. decode current instruction (All without memory capable within 1 clock cycle)
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1. decode current instruction (All without memory capable within 1 clock cycle)
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