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Line 43... |
short list of instructions: (not final, still planning)
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short list of instructions: (not final, still planning)
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immediates:
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immediates:
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1. move reg, immediate
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1. move reg, immediate
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2. move [reg], immediate
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2. move [reg], immediate
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3. push and move reg, immediate (or call immediate)
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3. push and move reg, immediate (or call immediate)
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4. push immediate
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4. move (relative) reg, immediate
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5. move (relative) reg, immediate
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mini-group 5. Root opcode is 5, register is to tell which opcode( up to 8). No register room, only immediate
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push immedate
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XX
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XX
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XX
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XX
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XX
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XX
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XX
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groups: (limited to 2 registers and no immediates. each group has 8 opcodes)
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groups: (limited to 2 registers and no immediates. each group has 8 opcodes)
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group 1:
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group 1:
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move(store) [reg],reg
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move(store) [reg],reg
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move(load) reg,[reg]
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move(load) reg,[reg]
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out reg1,reg2 (output to port reg1 value reg2)
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out reg1,reg2 (output to port reg1 value reg2)
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in reg1,reg2 (input from port reg2 and store in reg1)
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in reg1,reg2 (input from port reg2 and store in reg1)
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pop reg
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XX
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push reg
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XX
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move segmentreg,reg
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move segmentreg,reg
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move reg,segmentreg
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move reg,segmentreg
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group 2:
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group 2:
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and reg1,reg2 (reg1=reg1 and reg2)
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and reg1,reg2 (reg1=reg1 and reg2)
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| Line 84... |
Line 93... |
push segmentreg
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push segmentreg
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pop segmentreg
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pop segmentreg
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push and move reg, reg (or call reg)
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push and move reg, reg (or call reg)
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exchange reg,reg
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exchange reg,reg
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exchange reg,seg
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exchange reg,seg
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clear TR
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XX
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Set TR
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XX
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group 5:
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group 5:
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increment reg
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XX
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decrement reg
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XX
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far jmp reg1, reg2 (CS=reg1 and IP=reg2)
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far jmp reg1, reg2 (CS=reg1 and IP=reg2)
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far call reg1,reg2
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far call reg1,reg2
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far jmp [reg] (first byte is CS, second byte is IP)
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far jmp [reg] (first byte is CS, second byte is IP)
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push extended segmentreg, reg (equivalent to push seg; push reg)
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push extended segmentreg, reg (equivalent to push seg; push reg)
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pop extended segmentreg, reg (equivalent to pop reg; pop seg)
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pop extended segmentreg, reg (equivalent to pop reg; pop seg)
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| Line 107... |
Line 116... |
enable carryover seg
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enable carryover seg
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disable carryover seg
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disable carryover seg
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mov relative reg, reg
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mov relative reg, reg
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exchange reg, reg
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exchange reg, reg
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super group: Super groups only have room for 1 register argument. Each subgroup has 8 opcodes, capable of 8 subgroups.
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subgroup 0:
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push reg
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pop reg
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set TR
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reset TR
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increment reg
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decrement reg
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set register bank 0
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set register bank 1
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subgroup 1:
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enable carryover seg
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disable carryover seg
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3 register instructions:
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3 register instructions:
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1. add reg1, reg2, reg3 (reg1=reg2+reg3)
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1. add reg1, reg2, reg3 (reg1=reg2+reg3)
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2. sub reg1, reg2, reg3
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2. sub reg1, reg2, reg3
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opcodes used: 13 of 16. 3 more opcodes available. Decide what to do with the room later.
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opcodes used: 14 of 16. 2 more opcodes available. Decide what to do with the room later.
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Possible canidates for opcode compression include
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Possible canidates for opcode compression include
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* Push immediate (room for 3 sub-opcodes)
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* equals 0 and not equals 0 (room for 7 sub-opcodes each) (not doing that because it'd screw with the easy ALU code
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* push and pop reg (room for 7 sub-opcodes each)
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* equals 0 and not equals 0 (room for 7 sub-opcodes each)
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* Set TR and Reset TR (room for 64 opcodes each)
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* increment and decrement reg (room for 7 opcodes each)
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* enable and disable carry over (room for 7 opcodes each)
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* set register bank 0 and 1 (room for 64 opcodes each)
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0 -nop (doesn't do a thing)
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1 -move immediate (only uses first byte)
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2 -move
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3 -push
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4 -push immediate
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5 -push and move (or call when acting on ip)
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6 -compare (is less than, is less than or equal, is greater than, is greater than or equal, is equal, is not equal) (6 conditions room for 2 more in extra)
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7 -add
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8 -subtract
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9 -bitwise operations (xor, or, and, shift right, shift left, not)
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x -multiply (if room)
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x -divide
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conditionals
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conditionals
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0 -- always
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0 -- always
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1 -- only if true
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1 -- only if true
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for only if false, there should basically be another compare or if applicable an always afterwards
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for only if false, there should basically be another compare or if applicable an always afterwards
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push
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pop
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move
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add
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sub
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limitations that shouldn't be passed with instructions
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limitations that shouldn't be passed with instructions
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* Doing 2 memory references
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* Doing 2 memory references
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* pushing a memory reference (equates to 2 memory references)
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* pushing a memory reference (equates to 2 memory references)
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Note it is possible however to read and write 16bits at one time to the memory to consecutive addresses.
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Note it is possible however to read and write 16bits at one time to the memory to consecutive addresses that are 16-bit aligned.
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segments:
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segments:
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DS is used in all "normal" memory references
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DS is used in all "normal" memory references
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SS is used in all push and pop instructions
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SS is used in all push and pop instructions
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| Line 238... |
Line 239... |
10011 Increment
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10011 Increment
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10010 Decrement
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10010 Decrement
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10100 Add
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10100 Add
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10101 Subtract
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10101 Subtract
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Alignment restrictions:
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In general, their is very few times that a full 16-bit read or 16-bit write is done. These are the times:
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* Extended push
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* Extended pop
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* instruction fetch
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Because of this, and because I want for 2 clock cycles to be the longest instruction, I must place some alignment restrictions on the CPU
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So, IP must be aligned to a 16-bit address (must be an even number). And SP must also be aligned to a 16-bit address.
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Though I don't plan on putting any "real" restriction to setting it to an odd address, nothing will actually work right.
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Stack Details:
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Because of the need for 16-bit writes and reads of the stack, even though we're usually only using 8-bit values, we end up pushing 2 bytes at one time always.
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Stack is oppositely done from the 8086. push X will move X to SS:SP and then increment SP by 2.
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Let's take an example program:
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--SS is 0
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mov sp, 10
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push 0xff
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after this, 0x00FF will be moved to SS:SP (0x0010) and then sp will be incremented by 2. If we push an 8-bit value, the value is put in the least-significant byte, and the MSB is 0
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On Reset:
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On reset, all general registers are set to 0
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CS is set to 1, IP is set to 0. SS is set to 2 and SP is set to 0.
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Carryover is set on CS and not set on SS. DS and ES is 0. TR is false.
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Register bank 0 is selected.
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Implemented opcode list:
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legend:
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r = register choice
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C = conditional portion
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s = segment register choice
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i = immediate data
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0000 rrrC iiii iiii
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mov reg, immediate
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