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[/] [tinycpu/] [trunk/] [docs/] [design.md.txt] - Diff between revs 19 and 21
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Rev 21 |
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On reset, all general registers are set to 0
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On reset, all general registers are set to 0
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CS is set to 1, IP is set to 0. SS is set to 2 and SP is set to 0.
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CS is set to 1, IP is set to 0. SS is set to 2 and SP is set to 0.
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Carryover is set on CS and not set on SS. DS and ES is 0. TR is false.
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Carryover is set on CS and not set on SS. DS and ES is 0. TR is false.
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Register bank 0 is selected.
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Register bank 0 is selected.
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Electrical operation:
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On power-on, RESET should be high for at least 2 clock cycles. HOLD can optionally be high as well after these two clock cycles.
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When HOLD is no longer needed, it should just be turned low and an extra clock cycle should be waited on for it to return to RESET state
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When RESET is held low, the processor will execute. It takes 3 clock cycles for the processor to "catch up" to actually executing instructions
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Implemented opcode list:
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Implemented opcode list:
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legend:
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legend:
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