URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] [tinycpu/] [trunk/] [docs/] [design.md.txt] - Diff between revs 34 and 39

Rev 34	Rev 39
Line 4...	Line 4...
`2. 16-bit address bus`	`2. 16-bit address bus`
`3. fixed 16-bit instruction length`	`3. fixed 16-bit instruction length`
`4. use a small amount of "rich" instructions to do powerful things`	`4. use a small amount of "rich" instructions to do powerful things`
`5. 1 instruction per clock cycle`	`5. 1 instruction per clock cycle`

	`I/O:`
	`I/O has been decided to use a memory mapped approach.`
	`Howto:`

	`Basically, absolute address 0-32 is reserved for ports. Right now there is only a Port0. This port is 8-bits long.`
	`Each even address is the port address. Each odd address is the bitmap for write or read for the port below it.`

	`So to make ports 7 to 4 write and 3 to 0 read, you'd assign 0xF0 to address 0x0001`



`BIG CHANGE:`	`BIG CHANGE:`
`So, apparently making a single-cycle CPU is extremely hard... so instead, we'll be striving for a 2-cycle CPU.`	`So, apparently making a single-cycle CPU is extremely hard... so instead, we'll be striving for a 2-cycle CPU.`
`Usual cycles:`	`Usual cycles:`
`1-cycle: mov, jmp, etc general data movement`	`1-cycle: mov, jmp, etc general data movement`
Line 345...	Line 355...
`001: pop reg`	`001: pop reg`
`001: mov reg, reg`	`001: mov reg, reg`
`010: mov reg, [reg]`	`010: mov reg, [reg]`
`011: mov [reg], reg`	`011: mov [reg], reg`