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Line 5... |
3. fixed 16-bit instruction length
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3. fixed 16-bit instruction length
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4. use a small amount of "rich" instructions to do powerful things
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4. use a small amount of "rich" instructions to do powerful things
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5. 1 instruction per clock cycle
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5. 1 instruction per clock cycle
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Register list:
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Register list:
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r0-r2 general purpose registers
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r0-r6 general purpose registers
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ip instruction pointer register (represented as r3)
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ip instruction pointer register (represented as r7)
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cs, ds, es, ss segment registers (code segment, data segment, extra segment, stack segment)
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cs, ds, es, ss segment registers (code segment, data segment, extra segment, stack segment)
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tr truth register for conditionals
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tr truth register for conditionals
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general opcode format
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general opcode format
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first byte:
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first byte:
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first 4 bits: actual instruction
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first 4 bits: actual instruction
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next 2 bits: (target) register
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next 3 bits: (target) register
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last 2 bits: conditional
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last 1 bit: conditional
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second byte:
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second byte:
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first 1 bit: use segment registers
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first 1 bit: second portion of condition (if not immediate) (1 for only if false)
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next 1 bit: exchange target and source register
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next 1 bit: unused
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next 2 bits: other register
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next 3 bits: other register
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next 1 bit: dereference first register for memory (respecting the "exchange" bit)
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last 3 bits: extra opcode information or third register. such as for ADD it could be target=source+third_register
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next 3 bits: extra opcode information(optional) or last two bits is third register (such as for ADD it could be target=source+third_register)
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...or second byte is immediate value
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...or second byte is immediate value
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For opcodes requiring 3 registers but without room, the target opcode is assume to be the second operation. Such as for AND, target=source AND target
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For opcodes requiring 3 registers but without room, the target opcode is assume to be the second operation. Such as for AND, target=source AND target
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short list of instructions: (not final, still planning)
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short list of instructions: (not final, still planning)
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immediates:
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1. move reg, immediate
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2. move [reg], immediate
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3. push and move reg, immediate (or call immediate)
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4. push immediate
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groups: (limited to 2 registers and no immediates. each group has 8 opcodes)
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group 1:
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move(store) [reg],reg
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move(load) reg,[reg]
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out reg1,reg2 (output to port reg1 value reg2)
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in reg1,reg2 (input from port reg2 and store in reg1)
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group 2:
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and reg1,reg2 (reg1=reg1 and reg2)
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or reg, reg
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xor reg,reg
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not reg1,reg2 (reg1=not reg2)
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left shift reg,reg
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right shift reg,reg
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rotate right reg,reg
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rotate left reg,reg
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group 3: compares
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is greater than reg1,reg2 (TR=reg1>reg2)
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is greater or equal to reg,reg
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is less than reg,reg
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is less than or equal to reg,reg
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is equal to reg,reg
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is not equal to reg,reg
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3 register instructions:
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1. add reg1, reg2, reg3 (reg1=reg2+reg3)
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2. sub reg1, reg2, reg3
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0 -nop (doesn't do a thing)
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0 -nop (doesn't do a thing)
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1 -move immediate (only uses first byte)
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1 -move immediate (only uses first byte)
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2 -move
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2 -move
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3 -push
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3 -push
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4 -push immediate
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4 -push immediate
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Line 86... |
x -multiply (if room)
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x -multiply (if room)
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x -divide
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x -divide
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conditionals
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conditionals
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00 -- always
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0 -- always
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01 -- if true
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1 -- only if true
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10 -- if false
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for only if false, there should basically be another compare or if applicable an always afterwards
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11 -- reserved/not used
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push
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push
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pop
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pop
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move
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move
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add
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add
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