| Line 21... |
Line 21... |
TR: out std_logic
|
TR: out std_logic
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);
|
);
|
end alu;
|
end alu;
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|
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architecture Behavioral of alu is
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architecture Behavioral of alu is
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signal TRData: std_logic;
|
|
begin
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begin
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TR <= TRData;
|
|
process(DataIn1, DataIn2, Op)
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process(DataIn1, DataIn2, Op)
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begin
|
begin
|
--TRData <='0'; --default
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TR <= '0';
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case Op is
|
case Op is
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--bitwise operations
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--bitwise operations
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when "00000" => --and
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when "00000" => --and
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DataOut <= DataIn1 and DataIn2;
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DataOut <= DataIn1 and DataIn2;
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when "00001" => --or
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when "00001" => --or
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| Line 49... |
Line 47... |
DataOut <= std_logic_vector(rotate_right(unsigned(DataIn1),to_integer(unsigned(DataIn2(2 downto 0)))));
|
DataOut <= std_logic_vector(rotate_right(unsigned(DataIn1),to_integer(unsigned(DataIn2(2 downto 0)))));
|
--comparisons
|
--comparisons
|
when "01000" => --greater than
|
when "01000" => --greater than
|
DataOut <= "00000000";
|
DataOut <= "00000000";
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if(to_integer(unsigned(DataIn1)) > to_integer(unsigned(DataIn2))) then
|
if(to_integer(unsigned(DataIn1)) > to_integer(unsigned(DataIn2))) then
|
TRData <= '1';
|
TR <= '1';
|
else
|
else
|
TRData <= '0';
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TR <= '0';
|
end if;
|
end if;
|
when "01001" => --greater than or equal
|
when "01001" => --greater than or equal
|
DataOut <= "00000000";
|
DataOut <= "00000000";
|
if(to_integer(unsigned(DataIn1)) >= to_integer(unsigned(DataIn2))) then
|
if(to_integer(unsigned(DataIn1)) >= to_integer(unsigned(DataIn2))) then
|
TRData <= '1';
|
TR <= '1';
|
else
|
else
|
TRData <= '0';
|
TR <= '0';
|
end if;
|
end if;
|
when "01010" => --less than
|
when "01010" => --less than
|
DataOut <= "00000000";
|
DataOut <= "00000000";
|
if(to_integer(unsigned(DataIn1)) < to_integer(unsigned(DataIn2))) then
|
if(to_integer(unsigned(DataIn1)) < to_integer(unsigned(DataIn2))) then
|
TRData <= '1';
|
TR <= '1';
|
else
|
else
|
TRData <= '0';
|
TR <= '0';
|
end if;
|
end if;
|
when "01011" => --less than or equal
|
when "01011" => --less than or equal
|
DataOut <= "00000000";
|
DataOut <= "00000000";
|
if(to_integer(unsigned(DataIn1)) <= to_integer(unsigned(DataIn2))) then
|
if(to_integer(unsigned(DataIn1)) <= to_integer(unsigned(DataIn2))) then
|
TRData <= '1';
|
TR <= '1';
|
else
|
else
|
TRData <= '0';
|
TR <= '0';
|
end if;
|
end if;
|
when "01100" => --equals to
|
when "01100" => --equals to
|
DataOut <= "00000000";
|
DataOut <= "00000000";
|
if(to_integer(unsigned(DataIn1)) = to_integer(unsigned(DataIn2))) then
|
if(to_integer(unsigned(DataIn1)) = to_integer(unsigned(DataIn2))) then
|
TRData <= '1';
|
TR <= '1';
|
else
|
else
|
TRData <= '0';
|
TR <= '0';
|
end if;
|
end if;
|
when "01101" => --not equal
|
when "01101" => --not equal
|
DataOut <= "00000000";
|
DataOut <= "00000000";
|
if(to_integer(unsigned(DataIn1)) /= to_integer(unsigned(DataIn2))) then
|
if(to_integer(unsigned(DataIn1)) /= to_integer(unsigned(DataIn2))) then
|
TRData <= '1';
|
TR <= '1';
|
else
|
else
|
TRData <= '0';
|
TR <= '0';
|
end if;
|
end if;
|
when "01110" => --equal to 0
|
when "01110" => --equal to 0
|
DataOut <= "00000000";
|
DataOut <= "00000000";
|
if(to_integer(unsigned(DataIn1)) = 0) then
|
if(to_integer(unsigned(DataIn1)) = 0) then
|
TRData <= '1';
|
TR <= '1';
|
else
|
else
|
TRData <= '0';
|
TR <= '0';
|
end if;
|
end if;
|
when "01111" => --not equal to 0
|
when "01111" => --not equal to 0
|
DataOut <= "00000000";
|
DataOut <= "00000000";
|
if(to_integer(unsigned(DataIn1)) /= 0) then
|
if(to_integer(unsigned(DataIn1)) /= 0) then
|
TRData <= '1';
|
TR <= '1';
|
else
|
else
|
TRData <= '0';
|
TR <= '0';
|
end if;
|
end if;
|
--other operations
|
--other operations
|
when "10000" => --set TR
|
when "10000" => --set TR
|
DataOut <= "00000000";
|
DataOut <= "00000000";
|
TRData <= '1';
|
TR <= '1';
|
when "10001" => --reset TR
|
when "10001" => --reset TR
|
DataOut <= "00000000";
|
DataOut <= "00000000";
|
TRData <= '0';
|
TR <= '0';
|
when "10010" => --increment
|
when "10010" => --increment
|
DataOut <= std_logic_vector(unsigned(DataIn1) + 1);
|
DataOut <= std_logic_vector(unsigned(DataIn1) + 1);
|
when "10011" => --decrement
|
when "10011" => --decrement
|
DataOut <= std_logic_vector(unsigned(DataIn1) - 1);
|
DataOut <= std_logic_vector(unsigned(DataIn1) - 1);
|
when "10100" => --add
|
when "10100" => --add
|
| Line 120... |
Line 118... |
when "10101" => --subtract
|
when "10101" => --subtract
|
DataOut <= std_logic_vector(unsigned(DataIn1) - unsigned(DataIn2));
|
DataOut <= std_logic_vector(unsigned(DataIn1) - unsigned(DataIn2));
|
|
|
when others =>
|
when others =>
|
DataOut <= "00000000";
|
DataOut <= "00000000";
|
TRData <= '1';
|
TR <= '1';
|
end case;
|
end case;
|
end process;
|
end process;
|
end Behavioral;
|
end Behavioral;
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No newline at end of file
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