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[/] [tinycpu/] [trunk/] [src/] [blockram.vhd] - Diff between revs 10 and 11

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Rev 10 Rev 11
Line 9... Line 9...
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
 
 
            --if WriteEnable(0) = '1' then
 
              --          di0 <= DataIn(7 downto 0);
 
               -- else
 
                        --di0 := RAM(conv_integer(Address))(7 downto 0);
 
               --         di0 <= do(7 downto 0);
 
                --end if;
 
                --if WriteEnable(1) = '1' then
 
                    --    di1 <= DataIn(15 downto 8);
 
                --else
 
                        --di1 <= RAM(conv_integer(Address))(15 downto 8);
 
                  --      di1 <= do(15 downto 8);
 
                --end if;
 
 
 
entity blockram is
entity blockram is
  port(
  port(
    Address: in std_logic_vector(7 downto 0); --memory address
    Address: in std_logic_vector(7 downto 0); --memory address
    WriteEnable: in std_logic_vector(1 downto 0); --write 1 byte at a time option
    WriteEnable: in std_logic_vector(1 downto 0); --write 1 byte at a time option
    Enable: in std_logic;
    Enable: in std_logic;
Line 34... Line 21...
    DataOut: out std_logic_vector(15 downto 0)
    DataOut: out std_logic_vector(15 downto 0)
  );
  );
end blockram;
end blockram;
 
 
architecture Behavioral of blockram is
architecture Behavioral of blockram is
    type ram_type is array (255 downto 0) of std_logic_vector (15 downto 0);
    type ram_type is array (255 downto 0) of std_logic_vector (7 downto 0);
    signal RAM: ram_type;
    signal RAM0: ram_type; --Spartan 3Es don't natively support byte-wide write enables, so we'll just emulate it with 2 banks of RAM
 
    signal RAM1: ram_type;
    signal di0, di1: std_logic_vector(7 downto 0);
    signal di0, di1: std_logic_vector(7 downto 0);
    signal do : std_logic_vector(15 downto 0);
    signal do : std_logic_vector(15 downto 0);
begin
begin
  di0 <= DataIn(7 downto 0) when WriteEnable(0)='1' else do(7 downto 0);
  di0 <= DataIn(7 downto 0) when WriteEnable(0)='1' else do(7 downto 0);
    di1 <= DataIn(15 downto 8) when WriteEnable(1)='1' else do(15 downto 8);
    di1 <= DataIn(15 downto 8) when WriteEnable(1)='1' else do(15 downto 8);
  process (Clock)
  process (Clock)
  begin
  begin
    if rising_edge(Clock) then
    if rising_edge(Clock) then
      if Enable = '1' then
      if Enable = '1' then
        if WriteEnable(0)='1' or WriteEnable(1)='1' then
        if WriteEnable(0)='1' then
          RAM(conv_integer(Address)) <= di1 & di0;
          RAM0(conv_integer(Address)) <= di0;
 
        else
 
          do(7 downto 0) <= RAM0(conv_integer(Address)) ;
 
        end if;
 
        if WriteEnable(1)='1' then
 
          RAM1(conv_integer(Address)) <= di1;
        else
        else
          do <= RAM(conv_integer(Address)) ;
          do(15 downto 8) <= RAM1(conv_integer(Address));
        end if;
        end if;
      end if;
      end if;
    end if;
    end if;
  end process;
  end process;
  DataOut <= do;
  DataOut <= do;

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