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Line 13... |
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entity blockram is
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entity blockram is
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port(
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port(
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Address: in std_logic_vector(7 downto 0); --memory address
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Address: in std_logic_vector(11 downto 0); --memory address
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WriteEnable: in std_logic; --write or read
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WriteEnable: in std_logic_vector(1 downto 0); --write 1 byte at a time option
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Enable: in std_logic;
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Enable: in std_logic;
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Clock: in std_logic;
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Clock: in std_logic;
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DataIn: in std_logic_vector(15 downto 0);
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DataIn: in std_logic_vector(15 downto 0);
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DataOut: out std_logic_vector(15 downto 0)
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DataOut: out std_logic_vector(15 downto 0)
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);
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);
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end blockram;
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end blockram;
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architecture Behavioral of blockram is
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architecture Behavioral of blockram is
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type ram_type is array (255 downto 0) of std_logic_vector (15 downto 0);
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type ram_type is array (4095 downto 0) of std_logic_vector (15 downto 0);
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signal RAM: ram_type;
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signal RAM: ram_type;
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signal di0, di1, do0, do1: std_logic_vector(7 downto 0); --data inputs and outputs for byte-enable
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begin
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begin
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process (WriteEnable,DataIn)
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begin
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if WriteEnable(0) = '1' then
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di0 <= DataIn(7 downto 0);
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else
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di0 <= RAM(conv_integer(Address))(7 downto 0);
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do0 <= RAM(conv_integer(Address))(7 downto 0);
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end if;
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if WriteEnable(1)= '1' then
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di1 <= DataIn(15 downto 8);
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else
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di1 <= RAM(conv_integer(Address))(15 downto 8);
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do1 <= RAM(conv_integer(Address))(15 downto 8);
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end if;
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end process;
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process (Clock)
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process (Clock)
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begin
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begin
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if rising_edge(Clock) then
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if rising_edge(Clock) then
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if Enable = '1' then
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if Enable = '1' then
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if WriteEnable = '1' then
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DataOut <= do1 & do0;
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RAM(conv_integer(Address)) <= DataIn;
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RAM(conv_integer(Address)) <= di1 & di0;
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end if;
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DataOut <= RAM(conv_integer(Address)) ;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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No newline at end of file
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No newline at end of file
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