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Line 8... |
EnableCarry: in std_logic; --When disabled, SegmentIn goes to SegmentOut
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EnableCarry: in std_logic; --When disabled, SegmentIn goes to SegmentOut
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DataIn: in std_logic_vector(7 downto 0);
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DataIn: in std_logic_vector(7 downto 0);
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SegmentIn: in std_logic_vector(7 downto 0);
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SegmentIn: in std_logic_vector(7 downto 0);
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Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
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Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
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DataOut: out std_logic_vector(7 downto 0);
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DataOut: out std_logic_vector(7 downto 0);
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SegmentOut: out std_logic_vector(7 downto 0)
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SegmentOut: out std_logic_vector(7 downto 0);
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Clock: in std_logic
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-- Debug: out std_logic_vector(8 downto 0)
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-- Debug: out std_logic_vector(8 downto 0)
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);
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);
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end carryover;
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end carryover;
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architecture Behavioral of carryover is
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architecture Behavioral of carryover is
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signal temp: std_logic_vector(8 downto 0);
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signal temp: std_logic_vector(8 downto 0) := "000000000";
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signal temp2: std_logic_vector(7 downto 0);
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begin
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begin
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--treat as unsigned because it doesn't actually matter for addition and just make carry and borrow correct
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--treat as unsigned because it doesn't actually matter for addition and just make carry and borrow correct
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process(DataIn, SegmentIn,Addend, EnableCarry)
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process(DataIn, SegmentIn,Addend, EnableCarry)
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begin
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begin
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--if rising_edge(Clock) then
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temp <= std_logic_vector(unsigned('0' & DataIn) + unsigned( Addend));
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temp <= std_logic_vector(unsigned('0' & DataIn) + unsigned( Addend));
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-- if ('1' and ((not Addend(7)) and DataIn(7) and temp(8)))='1' then
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-- if ('1' and ((not Addend(7)) and DataIn(7) and temp(8)))='1' then
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if (EnableCarry and ((not Addend(7)) and DataIn(7) and not temp(8)))='1' then
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if (EnableCarry and ((not Addend(7)) and DataIn(7) and not temp(8)))='1' then
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SegmentOut <= std_logic_vector(unsigned(SegmentIn)+1);
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SegmentOut <= std_logic_vector(unsigned(SegmentIn)+1);
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elsif (EnableCarry and (Addend(7) and not DataIn(7) and temp(8)))='1' then
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elsif (EnableCarry and (Addend(7) and not DataIn(7) and temp(8)))='1' then
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SegmentOut <= std_logic_vector(unsigned(SegmentIn)-1);
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SegmentOut <= std_logic_vector(unsigned(SegmentIn)-1);
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else
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else
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SegmentOut <= SegmentIn;
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SegmentOut <= SegmentIn;
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end if;
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end if;
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--end if;
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end process;
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end process;
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--Debug <= Temp;
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--Debug <= Temp;
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DataOut <= temp(7 downto 0);
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DataOut <= temp(7 downto 0);
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end Behavioral;
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end Behavioral;
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