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[/] [tinycpu/] [trunk/] [src/] [carryover.vhd] - Diff between revs 16 and 21

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Rev 16 Rev 21
Line 8... Line 8...
    EnableCarry: in std_logic; --When disabled, SegmentIn goes to SegmentOut
    EnableCarry: in std_logic; --When disabled, SegmentIn goes to SegmentOut
    DataIn: in std_logic_vector(7 downto 0);
    DataIn: in std_logic_vector(7 downto 0);
    SegmentIn: in std_logic_vector(7 downto 0);
    SegmentIn: in std_logic_vector(7 downto 0);
    Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
    Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
    DataOut: out std_logic_vector(7 downto 0);
    DataOut: out std_logic_vector(7 downto 0);
    SegmentOut: out std_logic_vector(7 downto 0)
    SegmentOut: out std_logic_vector(7 downto 0);
 
    Clock: in std_logic
--    Debug: out std_logic_vector(8 downto 0)
--    Debug: out std_logic_vector(8 downto 0)
   );
   );
end carryover;
end carryover;
 
 
architecture Behavioral of carryover is
architecture Behavioral of carryover is
  signal temp: std_logic_vector(8 downto 0);
  signal temp: std_logic_vector(8 downto 0) := "000000000";
 
  signal temp2: std_logic_vector(7 downto 0);
begin
begin
  --treat as unsigned because it doesn't actually matter for addition and just make carry and borrow correct
  --treat as unsigned because it doesn't actually matter for addition and just make carry and borrow correct
  process(DataIn, SegmentIn,Addend, EnableCarry)
  process(DataIn, SegmentIn,Addend, EnableCarry)
 
 
  begin
  begin
 
    --if rising_edge(Clock) then
    temp <= std_logic_vector(unsigned('0' & DataIn) + unsigned( Addend));
    temp <= std_logic_vector(unsigned('0' & DataIn) + unsigned( Addend));
--    if ('1' and ((not Addend(7)) and DataIn(7) and temp(8)))='1' then 
--    if ('1' and ((not Addend(7)) and DataIn(7) and temp(8)))='1' then 
    if (EnableCarry and ((not Addend(7)) and DataIn(7) and not temp(8)))='1' then
    if (EnableCarry and ((not Addend(7)) and DataIn(7) and not temp(8)))='1' then
      SegmentOut <= std_logic_vector(unsigned(SegmentIn)+1);
      SegmentOut <= std_logic_vector(unsigned(SegmentIn)+1);
    elsif (EnableCarry and (Addend(7) and not DataIn(7) and temp(8)))='1' then
    elsif (EnableCarry and (Addend(7) and not DataIn(7) and temp(8)))='1' then
      SegmentOut <= std_logic_vector(unsigned(SegmentIn)-1);
      SegmentOut <= std_logic_vector(unsigned(SegmentIn)-1);
    else
    else
      SegmentOut <= SegmentIn;
      SegmentOut <= SegmentIn;
    end if;
    end if;
 
    --end if;
  end process;
  end process;
  --Debug <= Temp;
  --Debug <= Temp;
  DataOut <= temp(7 downto 0);
  DataOut <= temp(7 downto 0);
end Behavioral;
end Behavioral;
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