| Line 12... |
Line 12... |
port(
|
port(
|
--memory interface
|
--memory interface
|
MemAddr: out std_logic_vector(15 downto 0); --memory address (in bytes)
|
MemAddr: out std_logic_vector(15 downto 0); --memory address (in bytes)
|
MemWW: out std_logic; --memory writeword
|
MemWW: out std_logic; --memory writeword
|
MemWE: out std_logic; --memory writeenable
|
MemWE: out std_logic; --memory writeenable
|
MemOut: in std_logic_vector(15 downto 0);
|
MemIn: in std_logic_vector(15 downto 0);
|
MemIn: out std_logic_vector(15 downto 0);
|
MemOut: out std_logic_vector(15 downto 0);
|
--general interface
|
--general interface
|
Clock: in std_logic;
|
Clock: in std_logic;
|
Reset: in std_logic; --When this is high, CPU will reset within 1 clock cycles.
|
Reset: in std_logic; --When this is high, CPU will reset within 1 clock cycles.
|
--Enable: in std_logic; --When this is high, the CPU executes as normal, when low the CPU stops at the next clock cycle(maintaining all state)
|
--Enable: in std_logic; --When this is high, the CPU executes as normal, when low the CPU stops at the next clock cycle(maintaining all state)
|
Hold: in std_logic; --when high, CPU pauses execution and places Memory interfaces into high impendance state so the memory can be used by other components
|
Hold: in std_logic; --when high, CPU pauses execution and places Memory interfaces into high impendance state so the memory can be used by other components
|
HoldAck: out std_logic; --when high, CPU acknowledged hold and buses are in high Z
|
HoldAck: out std_logic; --when high, CPU acknowledged hold and buses are in high Z
|
--todo: port interface
|
--todo: port interface
|
|
|
--debug ports:
|
--debug ports:
|
DebugIR: out std_logic_vector(15 downto 0); --current instruction
|
DebugIR: out std_logic_vector(15 downto 0); --current instruction
|
DebugIP: out std_logic_vector(15 downto 0); --current IP
|
DebugIP: out std_logic_vector(7 downto 0); --current IP
|
DebugCS: out std_logic_vector(15 downto 0); --current code segment
|
DebugCS: out std_logic_vector(7 downto 0); --current code segment
|
DebugTR: out std_logic; --current value of TR
|
DebugTR: out std_logic; --current value of TR
|
|
DebugR0: out std_logic_vector(7 downto 0)
|
);
|
);
|
end core;
|
end core;
|
|
|
architecture Behavioral of core is
|
architecture Behavioral of core is
|
component fetch is
|
component fetch is
|
| Line 83... |
Line 84... |
FirstFetch,
|
FirstFetch,
|
Execute,
|
Execute,
|
WaitForMemory,
|
WaitForMemory,
|
HoldMemory
|
HoldMemory
|
);
|
);
|
signal state: ProcessState;
|
signal state: ProcessorState;
|
signal HeldState: ProcessState; --state the processor was in when HOLD was activated
|
signal HeldState: ProcessorState; --state the processor was in when HOLD was activated
|
|
|
--carryout signals
|
--carryout signals
|
signal CarryCS: std_logic;
|
signal CarryCS: std_logic;
|
signal CarrySS: std_logic;
|
signal CarrySS: std_logic;
|
signal IPAddend: std_logic_vector(7 downto 0);
|
signal IPAddend: std_logic_vector(7 downto 0);
|
| Line 114... |
Line 115... |
signal opreg1: std_logic_vector(2 downto 0);
|
signal opreg1: std_logic_vector(2 downto 0);
|
signal opreg2: std_logic_vector(2 downto 0);
|
signal opreg2: std_logic_vector(2 downto 0);
|
signal opreg3: std_logic_vector(2 downto 0);
|
signal opreg3: std_logic_vector(2 downto 0);
|
signal opseges: std_logic; --use ES segment
|
signal opseges: std_logic; --use ES segment
|
|
|
|
signal fetcheraddress: std_logic_vector(15 downto 0);
|
begin
|
begin
|
reg: port map registerfile(
|
reg: registerfile port map(
|
WriteEnable => regWE,
|
WriteEnable => regWE,
|
DataIn => regIn,
|
DataIn => regIn,
|
Clock => Clock,
|
Clock => Clock,
|
DataOut => regOut
|
DataOut => regOut
|
);
|
);
|
carryovercs: port map carryover(
|
carryovercs: carryover port map(
|
EnableCarry => CarryCS,
|
EnableCarry => CarryCS,
|
DataIn => regOut(REGIP);
|
DataIn => regOut(REGIP),
|
SegmentIn => regOut(REGCS);
|
SegmentIn => regOut(REGCS),
|
Addend => IPAddend;
|
Addend => IPAddend,
|
DataOut => IPCarryOut;
|
DataOut => IPCarryOut,
|
SegmentOut => CSCarryOut;\
|
SegmentOut => CSCarryOut
|
);
|
);
|
fetcher: port map fetch(
|
fetcher: fetch port map(
|
Enable => fetchEN,
|
Enable => fetchEN,
|
AddressIn => regOut(REGCS) & regOut(REGIP),
|
AddressIn => fetcheraddress,
|
Clock => Clock,
|
Clock => Clock,
|
DataIn => MemIn,
|
DataIn => MemIn,
|
IROut => IR,
|
IROut => IR,
|
AddressOut => MemAddr --this component supports tristate, so no worries about an intermediate signal
|
AddressOut => MemAddr --this component supports tristate, so no worries about an intermediate signal
|
);
|
);
|
|
fetcheraddress <= regOut(REGCS) & regOut(REGIP);
|
|
|
|
|
|
--opcode shortcuts
|
opmain <= IR(15 downto 12);
|
opmain <= IR(15 downto 12);
|
opimmd <= IR(7 downto 0);
|
opimmd <= IR(7 downto 0);
|
opcond1 <= IR(8);
|
opcond1 <= IR(8);
|
opcond2 <= IR(7);
|
opcond2 <= IR(7);
|
opreg1 <= IR(11 downto 9);
|
opreg1 <= IR(11 downto 9);
|
opreg3 <= IR(2 downto 0);
|
opreg3 <= IR(2 downto 0);
|
opreg2 <= IR(5 downto 3);
|
opreg2 <= IR(5 downto 3);
|
opseges <= IR(6);
|
opseges <= IR(6);
|
|
--debug ports
|
|
DebugCS <= regOut(REGCS);
|
|
DebugIP <= regOut(REGIP);
|
|
DebugR0 <= regOut(0);
|
|
DebugIR <= IR;
|
|
|
|
|
|
|
states: process()
|
|
|
states: process(Clock, reset, hold, state)
|
begin
|
begin
|
if rising_edge(Clock) then
|
if rising_edge(Clock) then
|
if reset='1' then
|
if reset='1' and hold='0' then
|
InReset <= '1';
|
InReset <= '1';
|
state <= ResetProcessor;
|
state <= ResetProcessor;
|
CarryCS <= '1';
|
HoldAck <= '0';
|
CarrySS <= '0';
|
|
--finish up
|
--finish up
|
elsif InReset='1' and reset='0' and Hold='0' then --reset is done, start executing
|
elsif InReset='1' and reset='0' and Hold='0' then --reset is done, start executing
|
InReset <= '0';
|
InReset <= '0';
|
state <= FirstFetch;
|
state <= FirstFetch;
|
fetchEN <= '1';
|
|
elsif Hold = '1' and (state=HoldMemory or state=Execute or state=ResetProcessor) then
|
elsif Hold = '1' and (state=HoldMemory or state=Execute or state=ResetProcessor) then
|
|
--do not hold immediately if waiting on memory or if waiting on the first fetch of an instruction after reset
|
state <= HoldMemory;
|
state <= HoldMemory;
|
HoldAck <= '1';
|
HoldAck <= '1';
|
FetchEN <= '0';
|
|
MemAddr <= "ZZZZZZZZZZZZZZZZ";
|
|
MemIn <= "ZZZZZZZZZZZZZZZZ";
|
|
elsif Hold='0' and state=HoldMemory then
|
elsif Hold='0' and state=HoldMemory then
|
state <= ResetProcessor when reset='1' else Execute;
|
if reset='1' or InReset='1' then
|
FetchEN <= '1';
|
state <= ResetProcessor;
|
|
else
|
|
state <= Execute;
|
|
end if;
|
elsif state=FirstFetch then --we have to let IR get loaded before we can execute.
|
elsif state=FirstFetch then --we have to let IR get loaded before we can execute.
|
|
--regWE <= (others => '0');
|
state <= Execute;
|
state <= Execute;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
decode: process()
|
decode: process(Clock, Hold, state, IR, inreset)
|
begin
|
begin
|
if rising_edge(Clock) and Hold='0' then
|
if rising_edge(Clock) then
|
if state=Execute then
|
if state=Execute then
|
|
fetchEN <= '1';
|
--reset to "usual"
|
--reset to "usual"
|
RegIn(REGIP) <= IPCarryOut;
|
RegIn(REGIP) <= IPCarryOut;
|
|
IPAddend <= x"02";
|
|
SPAddend <= x"00"; --no addend unless pushing or popping
|
RegIn(REGCS) <= CSCarryOut;
|
RegIn(REGCS) <= CSCarryOut;
|
RegWE <= (others => '0');
|
RegWE <= (others => '0');
|
|
MemWE <= '0';
|
|
MemWW <= '0';
|
|
|
--actual decoding
|
--actual decoding
|
case opmain is
|
case opmain is
|
when "0000" => --mov reg,imm
|
when "0000" => --mov reg,imm
|
RegIn(to_integer(unsigned(opreg1))) <= opimmd;
|
RegIn(to_integer(unsigned(opreg1))) <= opimmd;
|
| Line 195... |
Line 213... |
when others =>
|
when others =>
|
--synthesis off
|
--synthesis off
|
report "Not implemented" severity error;
|
report "Not implemented" severity error;
|
--synthesis on
|
--synthesis on
|
end case;
|
end case;
|
|
elsif state=ResetProcessor then
|
|
CarryCS <= '1';
|
|
CarrySS <= '0';
|
|
regWE <= (others => '1');
|
|
regIn <= (others => "00000000");
|
|
regIn(REGCS) <= x"01";
|
|
fetchEN <= '1';
|
|
elsif InReset='1' and hold='0' then
|
|
fetchEN <= '1';
|
|
elsif state=HoldMemory then
|
|
FetchEN <= '0';
|
|
MemAddr <= "ZZZZZZZZZZZZZZZZ";
|
|
MemOut <= "ZZZZZZZZZZZZZZZZ";
|
|
MemWE <= 'Z';
|
|
MemWW <= 'Z';
|
|
elsif state=FirstFetch then
|
|
fetchEN <= '1'; --already enabled, but anyway
|
|
elsif state=HoldMemory and hold='0' then
|
|
fetchEN <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
