| Line 58... |
Line 58... |
EnableCarry: in std_logic; --When disabled, SegmentIn goes to SegmentOut
|
EnableCarry: in std_logic; --When disabled, SegmentIn goes to SegmentOut
|
DataIn: in std_logic_vector(7 downto 0);
|
DataIn: in std_logic_vector(7 downto 0);
|
SegmentIn: in std_logic_vector(7 downto 0);
|
SegmentIn: in std_logic_vector(7 downto 0);
|
Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
|
Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
|
DataOut: out std_logic_vector(7 downto 0);
|
DataOut: out std_logic_vector(7 downto 0);
|
SegmentOut: out std_logic_vector(7 downto 0)
|
SegmentOut: out std_logic_vector(7 downto 0);
|
|
Clock: in std_logic
|
);
|
);
|
end component;
|
end component;
|
component registerfile is
|
component registerfile is
|
port(
|
port(
|
WriteEnable: in regwritetype;
|
WriteEnable: in regwritetype;
|
| Line 79... |
Line 80... |
constant REGDS: integer := 13;
|
constant REGDS: integer := 13;
|
constant REGCS: integer := 12;
|
constant REGCS: integer := 12;
|
|
|
type ProcessorState is (
|
type ProcessorState is (
|
ResetProcessor,
|
ResetProcessor,
|
FirstFetch,
|
FirstFetch1, --the fetcher needs two clock cycles to catch up
|
|
FirstFetch2,
|
Execute,
|
Execute,
|
WaitForMemory,
|
WaitForMemory,
|
HoldMemory
|
HoldMemory
|
);
|
);
|
signal state: ProcessorState;
|
signal state: ProcessorState;
|
| Line 125... |
Line 127... |
Clock => Clock,
|
Clock => Clock,
|
DataOut => regOut
|
DataOut => regOut
|
);
|
);
|
carryovercs: carryover port map(
|
carryovercs: carryover port map(
|
EnableCarry => CarryCS,
|
EnableCarry => CarryCS,
|
DataIn => regOut(REGIP),
|
DataIn => regIn(REGIP),
|
SegmentIn => regOut(REGCS),
|
SegmentIn => regIn(REGCS),
|
Addend => IPAddend,
|
Addend => IPAddend,
|
DataOut => IPCarryOut,
|
DataOut => IPCarryOut,
|
SegmentOut => CSCarryOut
|
SegmentOut => CSCarryOut,
|
|
Clock => Clock
|
);
|
);
|
fetcher: fetch port map(
|
fetcher: fetch port map(
|
Enable => fetchEN,
|
Enable => fetchEN,
|
AddressIn => fetcheraddress,
|
AddressIn => fetcheraddress,
|
Clock => Clock,
|
Clock => Clock,
|
DataIn => MemIn,
|
DataIn => MemIn,
|
IROut => IR,
|
IROut => IR,
|
AddressOut => MemAddr --this component supports tristate, so no worries about an intermediate signal
|
AddressOut => MemAddr --this component supports tristate, so no worries about an intermediate signal
|
);
|
);
|
fetcheraddress <= regOut(REGCS) & regOut(REGIP);
|
fetcheraddress <= regIn(REGCS) & regIn(REGIP);
|
|
|
|
|
--opcode shortcuts
|
--opcode shortcuts
|
opmain <= IR(15 downto 12);
|
opmain <= IR(15 downto 12);
|
opimmd <= IR(7 downto 0);
|
opimmd <= IR(7 downto 0);
|
| Line 159... |
Line 162... |
DebugR0 <= regOut(0);
|
DebugR0 <= regOut(0);
|
DebugIR <= IR;
|
DebugIR <= IR;
|
|
|
|
|
|
|
|
decode: process(Clock, Hold, state, IR, inreset, reset, regin, regout, IPCarryOut, CSCarryOut)
|
states: process(Clock, reset, hold, state)
|
|
begin
|
begin
|
if rising_edge(Clock) then
|
if rising_edge(Clock) then
|
|
|
|
--states
|
if reset='1' and hold='0' then
|
if reset='1' and hold='0' then
|
InReset <= '1';
|
InReset <= '1';
|
state <= ResetProcessor;
|
state <= ResetProcessor;
|
HoldAck <= '0';
|
HoldAck <= '0';
|
|
CarryCS <= '1';
|
|
CarrySS <= '0';
|
|
regWE <= (others => '1');
|
|
regIn <= (others => "00000000");
|
|
regIn(REGCS) <= x"01";
|
|
IPAddend <= x"00";
|
|
fetchEN <= '1';
|
--finish up
|
--finish up
|
elsif InReset='1' and reset='0' and Hold='0' then --reset is done, start executing
|
elsif InReset='1' and reset='0' and Hold='0' then --reset is done, start executing
|
InReset <= '0';
|
InReset <= '0';
|
state <= FirstFetch;
|
fetchEN <= '1';
|
|
state <= FirstFetch1;
|
elsif Hold = '1' and (state=HoldMemory or state=Execute or state=ResetProcessor) then
|
elsif Hold = '1' and (state=HoldMemory or state=Execute or state=ResetProcessor) then
|
--do not hold immediately if waiting on memory or if waiting on the first fetch of an instruction after reset
|
--do not hold immediately if waiting on memory or if waiting on the first fetch of an instruction after reset
|
state <= HoldMemory;
|
state <= HoldMemory;
|
HoldAck <= '1';
|
HoldAck <= '1';
|
|
FetchEN <= '0';
|
|
MemAddr <= "ZZZZZZZZZZZZZZZZ";
|
|
MemOut <= "ZZZZZZZZZZZZZZZZ";
|
|
MemWE <= 'Z';
|
|
MemWW <= 'Z';
|
elsif Hold='0' and state=HoldMemory then
|
elsif Hold='0' and state=HoldMemory then
|
if reset='1' or InReset='1' then
|
if reset='1' or InReset='1' then
|
state <= ResetProcessor;
|
state <= ResetProcessor;
|
else
|
else
|
state <= Execute;
|
state <= Execute;
|
end if;
|
end if;
|
elsif state=FirstFetch then --we have to let IR get loaded before we can execute.
|
FetchEN <= '1';
|
|
elsif state=FirstFetch1 then --we have to let IR get loaded before we can execute.
|
--regWE <= (others => '0');
|
--regWE <= (others => '0');
|
|
fetchEN <= '1'; --already enabled, but anyway
|
|
regWE <= (others => '0');
|
|
state <= FirstFetch2;
|
|
elsif state=FirstFetch2 then
|
state <= Execute;
|
state <= Execute;
|
|
IPAddend <= x"02";
|
|
SPAddend <= x"00"; --no addend unless pushing or popping
|
|
RegWE <= (others => '0');
|
|
regIn(REGIP) <= IPCarryOut;
|
|
regWE(REGIP) <= '1';
|
|
regWE(REGCS) <= '1';
|
|
regIn(REGCS) <= CSCarryOut;
|
end if;
|
end if;
|
|
|
end if;
|
|
end process;
|
|
|
|
decode: process(Clock, Hold, state, IR, inreset)
|
|
begin
|
|
if rising_edge(Clock) then
|
|
if state=Execute then
|
if state=Execute then
|
fetchEN <= '1';
|
fetchEN <= '1';
|
--reset to "usual"
|
--reset to "usual"
|
RegIn(REGIP) <= IPCarryOut;
|
|
IPAddend <= x"02";
|
IPAddend <= x"02";
|
SPAddend <= x"00"; --no addend unless pushing or popping
|
SPAddend <= x"00"; --no addend unless pushing or popping
|
RegIn(REGCS) <= CSCarryOut;
|
|
RegWE <= (others => '0');
|
RegWE <= (others => '0');
|
|
regIn(REGIP) <= IPCarryOut;
|
|
regWE(REGIP) <= '1';
|
|
regWE(REGCS) <= '1';
|
|
regIn(REGCS) <= CSCarryOut;
|
|
|
MemWE <= '0';
|
MemWE <= '0';
|
MemWW <= '0';
|
MemWW <= '0';
|
|
|
--actual decoding
|
--actual decoding
|
case opmain is
|
case opmain is
|
| Line 213... |
Line 240... |
when others =>
|
when others =>
|
--synthesis off
|
--synthesis off
|
report "Not implemented" severity error;
|
report "Not implemented" severity error;
|
--synthesis on
|
--synthesis on
|
end case;
|
end case;
|
elsif state=ResetProcessor then
|
|
CarryCS <= '1';
|
|
CarrySS <= '0';
|
|
regWE <= (others => '1');
|
|
regIn <= (others => "00000000");
|
|
regIn(REGCS) <= x"01";
|
|
fetchEN <= '1';
|
|
elsif InReset='1' and hold='0' then
|
|
fetchEN <= '1';
|
|
elsif state=HoldMemory then
|
|
FetchEN <= '0';
|
|
MemAddr <= "ZZZZZZZZZZZZZZZZ";
|
|
MemOut <= "ZZZZZZZZZZZZZZZZ";
|
|
MemWE <= 'Z';
|
|
MemWW <= 'Z';
|
|
elsif state=FirstFetch then
|
|
fetchEN <= '1'; --already enabled, but anyway
|
|
elsif state=HoldMemory and hold='0' then
|
|
fetchEN <= '1';
|
|
end if;
|
end if;
|
|
|
|
|
|
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
|
|
