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signal regbank: std_logic;
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signal regbank: std_logic;
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signal fetcheraddress: std_logic_vector(15 downto 0);
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signal fetcheraddress: std_logic_vector(15 downto 0);
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--temporary signals
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signal tempreg1: std_logic_vector(3 downto 0);
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signal bankreg1: std_logic_vector(3 downto 0); --these signals have register bank stuff baked in
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signal tempreg2: std_logic_vector(3 downto 0);
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signal bankreg2: std_logic_vector(3 downto 0);
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signal tempreg3: std_logic_vector(3 downto 0);
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signal bankreg3: std_logic_vector(3 downto 0);
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signal FetchMemAddr: std_logic_vector(15 downto 0);
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signal FetchMemAddr: std_logic_vector(15 downto 0);
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begin
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begin
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reg: registerfile port map(
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reg: registerfile port map(
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Line 195... |
opimmd <= IR(7 downto 0);
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opimmd <= IR(7 downto 0);
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opcond1 <= IR(8);
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opcond1 <= IR(8);
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opcond2 <= IR(7);
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opcond2 <= IR(7);
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opreg1 <= IR(11 downto 9);
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opreg1 <= IR(11 downto 9);
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opreg3 <= IR(2 downto 0);
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opreg3 <= IR(2 downto 0);
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opreg2 <= IR(5 downto 3);
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opreg2 <= IR(6 downto 4);
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opseges <= IR(6);
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opseges <= IR(3);
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--debug ports
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--debug ports
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DebugCS <= regOut(REGCS);
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DebugCS <= regOut(REGCS);
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DebugIP <= regOut(REGIP);
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DebugIP <= regOut(REGIP);
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DebugR0 <= regOut(0);
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DebugR0 <= regOut(0);
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DebugIR <= IR;
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DebugIR <= IR;
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DebugTR <= TR;
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DebugTR <= TR;
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--register addresses with registerbank baked in
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--register addresses with registerbank baked in
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tempreg1 <= ('1' & opreg1) when (regbank='1' and opreg1(2)='0') else '0' & opreg1;
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bankreg1 <= ('1' & opreg1) when (regbank='1' and opreg1(2)='0') else '0' & opreg1;
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tempreg2 <= ('1' & opreg2) when (regbank='1' and opreg2(2)='0') else '0' & opreg2;
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bankreg2 <= ('1' & opreg2) when (regbank='1' and opreg2(2)='0') else '0' & opreg2;
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tempreg3 <= ('1' & opreg3) when (regbank='1' and opreg3(2)='0') else '0' & opreg3;
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bankreg3 <= ('1' & opreg3) when (regbank='1' and opreg3(2)='0') else '0' & opreg3;
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decode: process(Clock, Hold, state, IR, inreset, reset, regin, regout, IPCarryOut, CSCarryOut)
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decode: process(Clock, Hold, state, IR, inreset, reset, regin, regout, IPCarryOut, CSCarryOut)
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begin
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begin
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--actual decoding
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--actual decoding
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if opcond1='0' or (opcond1='1' and TR='1') then
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if opcond1='0' or (opcond1='1' and TR='1') then
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case opmain is
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case opmain is
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when "0000" => --mov reg,imm
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when "0000" => --mov reg,imm
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regIn(to_integer(unsigned(tempreg1))) <= opimmd;
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regIn(to_integer(unsigned(bankreg1))) <= opimmd;
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regWE(to_integer(unsigned(tempreg1))) <= '1';
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regWE(to_integer(unsigned(bankreg1))) <= '1';
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when "0001" => --mov [reg],imm
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when "0001" => --mov [reg],imm
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OpAddress <= regOut(REGDS) & regOut(to_integer(unsigned(tempreg1)));
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OpAddress <= regOut(REGDS) & regOut(to_integer(unsigned(bankreg1)));
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OpWE <= '1';
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OpWE <= '1';
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OpData <= x"00" & opimmd;
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OpData <= x"00" & opimmd;
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OpWW <= '0';
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OpWW <= '0';
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state <= WaitForMemory;
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state <= WaitForMemory;
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IPAddend <= x"00"; --disable all this because we have to wait a cycle to write memory
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IPAddend <= x"00"; --disable all this because we have to wait a cycle to write memory
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FetchEN <= '0';
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FetchEN <= '0';
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when "0011" => --group 3 comparisons
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AluOp <= "01" & opreg3; --nothing hard here, ALU does it all for us
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AluIn1 <= regOut(to_integer(unsigned(opreg1)));
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AluIn2 <= regOut(to_integer(unsigned(opreg2)));
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when "0100" => --group 4 bitwise operations
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AluOp <= "00" & opreg3; --nothing hard here, ALU does it all for us
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AluIn1 <= regOut(to_integer(unsigned(opreg1)));
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AluIn2 <= regOut(to_integer(unsigned(opreg2)));
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regIn(to_integer(unsigned(opreg1))) <= AluOut;
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regWE(to_integer(unsigned(opreg1))) <= '1';
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when others =>
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when others =>
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--synthesis off
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--synthesis off
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report "Not implemented" severity error;
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report "Not implemented" severity error;
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--synthesis on
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--synthesis on
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end case;
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end case;
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