| Line 141... |
Line 141... |
signal bankreg1: std_logic_vector(3 downto 0); --these signals have register bank stuff baked in
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signal bankreg1: std_logic_vector(3 downto 0); --these signals have register bank stuff baked in
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signal bankreg2: std_logic_vector(3 downto 0);
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signal bankreg2: std_logic_vector(3 downto 0);
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signal bankreg3: std_logic_vector(3 downto 0);
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signal bankreg3: std_logic_vector(3 downto 0);
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signal FetchMemAddr: std_logic_vector(15 downto 0);
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signal FetchMemAddr: std_logic_vector(15 downto 0);
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signal UsuallySS: std_logic_vector(3 downto 0);
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signal UsuallyDS: std_logic_vector(3 downto 0);
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begin
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begin
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reg: registerfile port map(
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reg: registerfile port map(
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WriteEnable => regWE,
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WriteEnable => regWE,
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DataIn => regIn,
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DataIn => regIn,
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Clock => Clock,
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Clock => Clock,
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| Line 207... |
Line 208... |
DebugTR <= TR;
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DebugTR <= TR;
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--register addresses with registerbank baked in
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--register addresses with registerbank baked in
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bankreg1 <= ('1' & opreg1) when (regbank='1' and opreg1(2)='0') else '0' & opreg1;
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bankreg1 <= ('1' & opreg1) when (regbank='1' and opreg1(2)='0') else '0' & opreg1;
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bankreg2 <= ('1' & opreg2) when (regbank='1' and opreg2(2)='0') else '0' & opreg2;
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bankreg2 <= ('1' & opreg2) when (regbank='1' and opreg2(2)='0') else '0' & opreg2;
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bankreg3 <= ('1' & opreg3) when (regbank='1' and opreg3(2)='0') else '0' & opreg3;
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bankreg3 <= ('1' & opreg3) when (regbank='1' and opreg3(2)='0') else '0' & opreg3;
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--UsuallySegment shortcuts (only used when not an immediate
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UsuallyDS <= "1101" when opseges='0' else "1110";
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UsuallySS <= "1111" when opseges='0' else "1110";
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foo: process(Clock, Hold, state, IR, inreset, reset, regin, regout, IPCarryOut, CSCarryOut)
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decode: process(Clock, Hold, state, IR, inreset, reset, regin, regout, IPCarryOut, CSCarryOut)
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begin
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begin
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if rising_edge(Clock) then
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if rising_edge(Clock) then
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--states
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--states
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if reset='1' and hold='0' then
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if reset='1' and hold='0' then
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| Line 271... |
Line 274... |
state <= Execute;
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state <= Execute;
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elsif state=WaitForMemory then
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elsif state=WaitForMemory then
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state <= Execute;
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state <= Execute;
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FetchEn <= '1';
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FetchEn <= '1';
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IpAddend <= x"02";
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IpAddend <= x"02";
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SpAddend <= x"00";
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end if;
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end if;
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if state=Execute then
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if state=Execute then
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fetchEN <= '1';
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fetchEN <= '1';
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Line 310... |
state <= WaitForMemory;
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state <= WaitForMemory;
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IPAddend <= x"00"; --disable all this because we have to wait a cycle to write memory
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IPAddend <= x"00"; --disable all this because we have to wait a cycle to write memory
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FetchEN <= '0';
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FetchEN <= '0';
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when "0011" => --group 3 comparisons
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when "0011" => --group 3 comparisons
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AluOp <= "01" & opreg3; --nothing hard here, ALU does it all for us
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AluOp <= "01" & opreg3; --nothing hard here, ALU does it all for us
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AluIn1 <= regOut(to_integer(unsigned(opreg1)));
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AluIn1 <= regOut(to_integer(unsigned(bankreg1)));
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AluIn2 <= regOut(to_integer(unsigned(opreg2)));
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AluIn2 <= regOut(to_integer(unsigned(bankreg2)));
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when "0100" => --group 4 bitwise operations
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when "0100" => --group 4 bitwise operations
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AluOp <= "00" & opreg3; --nothing hard here, ALU does it all for us
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AluOp <= "00" & opreg3; --nothing hard here, ALU does it all for us
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AluIn1 <= regOut(to_integer(unsigned(opreg1)));
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AluIn1 <= regOut(to_integer(unsigned(bankreg1)));
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AluIn2 <= regOut(to_integer(unsigned(opreg2)));
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AluIn2 <= regOut(to_integer(unsigned(bankreg2)));
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regIn(to_integer(unsigned(opreg1))) <= AluOut;
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regIn(to_integer(unsigned(bankreg1))) <= AluOut;
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regWE(to_integer(unsigned(opreg1))) <= '1';
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regWE(to_integer(unsigned(bankreg1))) <= '1';
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when "0101" => --group 5
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case opreg3 is
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when "000" => --subgroup 5-0
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case opreg2 is
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when "000" => --push reg
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SpAddend <= x"02"; --set SP to increment
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OpAddress <= regOut(to_integer(unsigned(UsuallySS))) & regOut(REGSP);
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OpWE <= '1';
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OpData <= x"00" & regOut(to_integer(unsigned(bankreg1)));
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OpWW <= '1';
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state <= WaitForMemory;
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IPAddend <= x"00";
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FetchEN <= '0';
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when "001" => --pop reg
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SPAddend <= x"FE"; --set SP to decrement
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OpAddress <= regOut(to_integer(unsigned(UsuallySS))) & regOut(REGSP);
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OpWE <= '0';
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regIn(to_integer(unsigned(bankreg1))) <= OpData(7 downto 0);
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OpWW <= '0';
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state <= WaitForMemory;
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IPAddend <= x"00";
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FetchEN <= '0';
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when others =>
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--synthesis off
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report "Not implemented subgroup 5-0" severity error;
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--synthesis on
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end case;
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when others =>
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--synthesis off
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report "Not implemented group 5" severity error;
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--synthesis on
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end case;
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when others =>
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when others =>
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--synthesis off
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--synthesis off
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report "Not implemented" severity error;
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report "Not implemented" severity error;
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--synthesis on
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--synthesis on
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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