| Line 85... |
Line 85... |
FirstFetch1, --the fetcher needs two clock cycles to catch up
|
FirstFetch1, --the fetcher needs two clock cycles to catch up
|
FirstFetch2,
|
FirstFetch2,
|
Firstfetch3,
|
Firstfetch3,
|
Execute,
|
Execute,
|
WaitForMemory,
|
WaitForMemory,
|
HoldMemory
|
HoldMemory,
|
|
WaitForAlu -- wait for settling is needed when using the ALU
|
);
|
);
|
signal state: ProcessorState;
|
signal state: ProcessorState;
|
signal HeldState: ProcessorState; --state the processor was in when HOLD was activated
|
signal HeldState: ProcessorState; --state the processor was in when HOLD was activated
|
|
|
--carryout signals
|
--carryout signals
|
| Line 143... |
Line 144... |
signal bankreg3: std_logic_vector(3 downto 0);
|
signal bankreg3: std_logic_vector(3 downto 0);
|
signal FetchMemAddr: std_logic_vector(15 downto 0);
|
signal FetchMemAddr: std_logic_vector(15 downto 0);
|
|
|
signal UsuallySS: std_logic_vector(3 downto 0);
|
signal UsuallySS: std_logic_vector(3 downto 0);
|
signal UsuallyDS: std_logic_vector(3 downto 0);
|
signal UsuallyDS: std_logic_vector(3 downto 0);
|
|
signal aluregisterout: std_logic_vector(3 downto 0);
|
begin
|
begin
|
reg: registerfile port map(
|
reg: registerfile port map(
|
WriteEnable => regWE,
|
WriteEnable => regWE,
|
DataIn => regIn,
|
DataIn => regIn,
|
Clock => Clock,
|
Clock => Clock,
|
| Line 275... |
Line 277... |
elsif state=WaitForMemory then
|
elsif state=WaitForMemory then
|
state <= Execute;
|
state <= Execute;
|
FetchEn <= '1';
|
FetchEn <= '1';
|
IpAddend <= x"02";
|
IpAddend <= x"02";
|
SpAddend <= x"00";
|
SpAddend <= x"00";
|
|
elsif state=WaitForAlu then
|
|
state <= Execute;
|
|
regIn(to_integer(unsigned(AluRegisterOut))) <= AluOut;
|
|
regWE(to_integer(unsigned(AluRegisterOut))) <= '1';
|
|
FetchEN <= '1';
|
|
IPAddend <= x"02";
|
|
SPAddend <= x"00";
|
end if;
|
end if;
|
|
|
|
|
if state=Execute then
|
if state=Execute then
|
fetchEN <= '1';
|
fetchEN <= '1';
|
| Line 313... |
Line 322... |
when "0011" => --group 3 comparisons
|
when "0011" => --group 3 comparisons
|
AluOp <= "01" & opreg3; --nothing hard here, ALU does it all for us
|
AluOp <= "01" & opreg3; --nothing hard here, ALU does it all for us
|
AluIn1 <= regOut(to_integer(unsigned(bankreg1)));
|
AluIn1 <= regOut(to_integer(unsigned(bankreg1)));
|
AluIn2 <= regOut(to_integer(unsigned(bankreg2)));
|
AluIn2 <= regOut(to_integer(unsigned(bankreg2)));
|
when "0100" => --group 4 bitwise operations
|
when "0100" => --group 4 bitwise operations
|
|
--setup wait state
|
|
State <= WaitForAlu;
|
|
FetchEN <= '0';
|
|
IPAddend <= x"00";
|
AluOp <= "00" & opreg3; --nothing hard here, ALU does it all for us
|
AluOp <= "00" & opreg3; --nothing hard here, ALU does it all for us
|
AluIn1 <= regOut(to_integer(unsigned(bankreg1)));
|
AluIn1 <= regOut(to_integer(unsigned(bankreg1)));
|
AluIn2 <= regOut(to_integer(unsigned(bankreg2)));
|
AluIn2 <= regOut(to_integer(unsigned(bankreg2)));
|
regIn(to_integer(unsigned(bankreg1))) <= AluOut;
|
AluRegisterOut <= bankreg1;
|
regWE(to_integer(unsigned(bankreg1))) <= '1';
|
--regIn(to_integer(unsigned(bankreg1))) <= AluOut;
|
|
--regWE(to_integer(unsigned(bankreg1))) <= '1';
|
when "0101" => --group 5
|
when "0101" => --group 5
|
case opreg3 is
|
case opreg3 is
|
when "000" => --subgroup 5-0
|
when "000" => --subgroup 5-0
|
case opreg2 is
|
case opreg2 is
|
when "000" => --push reg
|
when "000" => --push reg
|
