| Line 113... |
Line 113... |
--alu signals
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--alu signals
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signal AluOp: std_logic_vector(4 downto 0);
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signal AluOp: std_logic_vector(4 downto 0);
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signal AluIn1: std_logic_vector(7 downto 0);
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signal AluIn1: std_logic_vector(7 downto 0);
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signal AluIn2: std_logic_vector(7 downto 0);
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signal AluIn2: std_logic_vector(7 downto 0);
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signal AluOut: std_logic_vector(7 downto 0);
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signal AluOut: std_logic_vector(7 downto 0);
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signal AluTR: std_logic;
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signal TR: std_logic;
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signal TR: std_logic;
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signal TRData: std_logic;
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signal UseAluTR: std_logic;
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--control signals
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--control signals
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signal InReset: std_logic;
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signal InReset: std_logic;
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signal OpAddress: std_logic_vector(15 downto 0); --memory address to use for operation of an instruction
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signal OpAddress: std_logic_vector(15 downto 0); --memory address to use for operation of an instruction
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signal OpData: std_logic_vector(15 downto 0); --data to write or will load to here
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signal OpData: std_logic_vector(15 downto 0); --data to write or will load to here
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| Line 183... |
Line 186... |
cpualu: alu port map(
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cpualu: alu port map(
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Op => AluOp,
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Op => AluOp,
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DataIn1 => AluIn1,
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DataIn1 => AluIn1,
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DataIn2 => AluIn2,
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DataIn2 => AluIn2,
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DataOut => AluOut,
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DataOut => AluOut,
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TR => TR
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TR => AluTR
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);
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);
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fetcheraddress <= regIn(REGCS) & regIn(REGIP);
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fetcheraddress <= regIn(REGCS) & regIn(REGIP);
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MemAddr <= OpAddress when state=WaitForMemory else FetchMemAddr;
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MemAddr <= OpAddress when state=WaitForMemory else FetchMemAddr;
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MemOut <= OpData when (state=WaitForMemory and OpWE='1') else "ZZZZZZZZZZZZZZZZ" when state=HoldMemory else x"0000";
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MemOut <= OpData when (state=WaitForMemory and OpWE='1') else "ZZZZZZZZZZZZZZZZ" when state=HoldMemory else x"0000";
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MemWE <= OpWE when state=WaitForMemory else 'Z' when state=HoldMemory else '0';
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MemWE <= OpWE when state=WaitForMemory else 'Z' when state=HoldMemory else '0';
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| Line 213... |
Line 216... |
bankreg2 <= ('1' & opreg2) when (regbank='1' and opreg2(2)='0') else '0' & opreg2;
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bankreg2 <= ('1' & opreg2) when (regbank='1' and opreg2(2)='0') else '0' & opreg2;
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bankreg3 <= ('1' & opreg3) when (regbank='1' and opreg3(2)='0') else '0' & opreg3;
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bankreg3 <= ('1' & opreg3) when (regbank='1' and opreg3(2)='0') else '0' & opreg3;
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--UsuallySegment shortcuts (only used when not an immediate
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--UsuallySegment shortcuts (only used when not an immediate
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UsuallyDS <= "1101" when opseges='0' else "1110";
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UsuallyDS <= "1101" when opseges='0' else "1110";
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UsuallySS <= "1111" when opseges='0' else "1110";
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UsuallySS <= "1111" when opseges='0' else "1110";
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TR <= TRData when UseAluTR='0' else AluTR;
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foo: process(Clock, Hold, state, IR, inreset, reset, regin, regout, IPCarryOut, CSCarryOut)
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foo: process(Clock, Hold, state, IR, inreset, reset, regin, regout, IPCarryOut, CSCarryOut)
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begin
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begin
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if rising_edge(Clock) then
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if rising_edge(Clock) then
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| Line 238... |
Line 241... |
fetchEN <= '1';
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fetchEN <= '1';
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OpData <= "ZZZZZZZZZZZZZZZZ";
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OpData <= "ZZZZZZZZZZZZZZZZ";
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OpAddress <= x"0000";
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OpAddress <= x"0000";
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OpWE <= '0';
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OpWE <= '0';
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opWW <= '0';
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opWW <= '0';
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TRData <= '0';
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UseAluTR <= '0';
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--finish up
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--finish up
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elsif InReset='1' and reset='0' and Hold='0' then --reset is done, start executing
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elsif InReset='1' and reset='0' and Hold='0' then --reset is done, start executing
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InReset <= '0';
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InReset <= '0';
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fetchEN <= '1';
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fetchEN <= '1';
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state <= FirstFetch1;
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state <= FirstFetch1;
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| Line 302... |
Line 307... |
regIn(REGSP) <= SPCarryOut; --with addend being 0, it'll just write SP to SP so it won't change, but this makes code easier for me
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regIn(REGSP) <= SPCarryOut; --with addend being 0, it'll just write SP to SP so it won't change, but this makes code easier for me
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regIn(REGSS) <= SSCarryOut;
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regIn(REGSS) <= SSCarryOut;
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regWE(REGSP) <= '1';
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regWE(REGSP) <= '1';
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regWE(REGSS) <= '1';
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regWE(REGSS) <= '1';
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OpAddress <= "ZZZZZZZZZZZZZZZZ";
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OpAddress <= "ZZZZZZZZZZZZZZZZ";
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if UseAluTR='1' then
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UseAluTR<='0';
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end if;
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--actual decoding
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--actual decoding
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if opcond1='0' or (opcond1='1' and TR='1') then
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if opcond1='0' or (opcond1='1' and TR='1') then
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case opmain is
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case opmain is
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when "0000" => --mov reg,imm
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when "0000" => --mov reg,imm
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regIn(to_integer(unsigned(bankreg1))) <= opimmd;
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regIn(to_integer(unsigned(bankreg1))) <= opimmd;
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| Line 318... |
Line 325... |
OpWW <= '0';
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OpWW <= '0';
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state <= WaitForMemory;
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state <= WaitForMemory;
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IPAddend <= x"00"; --disable all this because we have to wait a cycle to write memory
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IPAddend <= x"00"; --disable all this because we have to wait a cycle to write memory
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FetchEN <= '0';
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FetchEN <= '0';
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when "0011" => --group 3 comparisons
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when "0011" => --group 3 comparisons
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TRData <= AluTR;
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UseAluTR <= '1';
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AluOp <= "01" & opreg3; --nothing hard here, ALU does it all for us
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AluOp <= "01" & opreg3; --nothing hard here, ALU does it all for us
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AluIn1 <= regOut(to_integer(unsigned(bankreg1)));
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AluIn1 <= regOut(to_integer(unsigned(bankreg1)));
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AluIn2 <= regOut(to_integer(unsigned(bankreg2)));
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AluIn2 <= regOut(to_integer(unsigned(bankreg2)));
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when "0100" => --group 4 bitwise operations
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when "0100" => --group 4 bitwise operations
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--setup wait state
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--setup wait state
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