| Line 121... |
Line 121... |
signal UseAluTR: std_logic;
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signal UseAluTR: std_logic;
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--control signals
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--control signals
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signal InReset: std_logic;
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signal InReset: std_logic;
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signal OpAddress: std_logic_vector(15 downto 0); --memory address to use for operation of an instruction
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signal OpAddress: std_logic_vector(15 downto 0); --memory address to use for operation of an instruction
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signal OpData: std_logic_vector(15 downto 0); --data to write or will load to here
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signal OpDataIn: std_logic_vector(15 downto 0);
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signal OpDataOut: std_logic_vector(15 downto 0);
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signal OpWW: std_logic;
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signal OpWW: std_logic;
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signal OpWE: std_logic;
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signal OpWE: std_logic;
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signal OpDestReg1: std_logic_vector(3 downto 0);
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signal OpUseReg2: std_logic;
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signal OpDestReg2: std_logic_vector(3 downto 0);
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--opcode shortcut signals
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--opcode shortcut signals
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signal opmain: std_logic_vector(3 downto 0);
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signal opmain: std_logic_vector(3 downto 0);
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signal opimmd: std_logic_vector(7 downto 0);
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signal opimmd: std_logic_vector(7 downto 0);
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signal opcond1: std_logic; --first conditional bit
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signal opcond1: std_logic; --first conditional bit
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| Line 147... |
Line 151... |
signal bankreg3: std_logic_vector(3 downto 0);
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signal bankreg3: std_logic_vector(3 downto 0);
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signal FetchMemAddr: std_logic_vector(15 downto 0);
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signal FetchMemAddr: std_logic_vector(15 downto 0);
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signal UsuallySS: std_logic_vector(3 downto 0);
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signal UsuallySS: std_logic_vector(3 downto 0);
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signal UsuallyDS: std_logic_vector(3 downto 0);
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signal UsuallyDS: std_logic_vector(3 downto 0);
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signal aluregisterout: std_logic_vector(3 downto 0);
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signal AluRegOut: std_logic_vector(3 downto 0);
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begin
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begin
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reg: registerfile port map(
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reg: registerfile port map(
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WriteEnable => regWE,
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WriteEnable => regWE,
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DataIn => regIn,
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DataIn => regIn,
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Clock => Clock,
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Clock => Clock,
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| Line 190... |
Line 194... |
DataOut => AluOut,
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DataOut => AluOut,
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TR => AluTR
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TR => AluTR
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);
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);
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fetcheraddress <= regIn(REGCS) & regIn(REGIP);
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fetcheraddress <= regIn(REGCS) & regIn(REGIP);
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MemAddr <= OpAddress when state=WaitForMemory else FetchMemAddr;
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MemAddr <= OpAddress when state=WaitForMemory else FetchMemAddr;
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MemOut <= OpData when (state=WaitForMemory and OpWE='1') else "ZZZZZZZZZZZZZZZZ" when state=HoldMemory else x"0000";
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MemOut <= OpDataOut when (state=WaitForMemory and OpWE='1') else "ZZZZZZZZZZZZZZZZ" when state=HoldMemory else x"0000";
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MemWE <= OpWE when state=WaitForMemory else 'Z' when state=HoldMemory else '0';
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MemWE <= OpWE when state=WaitForMemory else 'Z' when state=HoldMemory else '0';
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MemWW <= OpWW when state=WaitForMemory else 'Z' when state=HoldMEmory else '0';
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MemWW <= OpWW when state=WaitForMemory else 'Z' when state=HoldMEmory else '0';
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OpData <= MemIn when (state=WaitForMemory and OpWE='0') else "ZZZZZZZZZZZZZZZZ";
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OpDataIn <= MemIn;
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--opcode shortcuts
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--opcode shortcuts
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opmain <= IR(15 downto 12);
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opmain <= IR(15 downto 12);
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opimmd <= IR(7 downto 0);
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opimmd <= IR(7 downto 0);
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opcond1 <= IR(8);
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opcond1 <= IR(8);
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opcond2 <= IR(7);
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opcond2 <= IR(7);
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| Line 232... |
Line 236... |
CarryCS <= '1';
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CarryCS <= '1';
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CarrySS <= '0';
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CarrySS <= '0';
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regWE <= (others => '1');
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regWE <= (others => '1');
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regIn <= (others => "00000000");
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regIn <= (others => "00000000");
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regIn(REGCS) <= x"01";
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regIn(REGCS) <= x"01";
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regIn(REGSS) <= x"02";
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IPAddend <= x"00";
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IPAddend <= x"00";
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SPAddend <= x"00";
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SPAddend <= x"00";
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AluOp <= "10001"; --reset TR in ALU
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AluOp <= "10001"; --reset TR in ALU
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regbank <= '0';
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regbank <= '0';
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fetchEN <= '1';
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fetchEN <= '1';
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OpData <= "ZZZZZZZZZZZZZZZZ";
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OpDataOut <= "ZZZZZZZZZZZZZZZZ";
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OpAddress <= x"0000";
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OpAddress <= x"0000";
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OpWE <= '0';
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OpWE <= '0';
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opWW <= '0';
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opWW <= '0';
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TRData <= '0';
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TRData <= '0';
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UseAluTR <= '0';
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UseAluTR <= '0';
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OpDestReg1<= x"0";
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OpDestReg2 <= x"0";
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OpUseReg2 <= '0';
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--finish up
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--finish up
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elsif InReset='1' and reset='0' and Hold='0' then --reset is done, start executing
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elsif InReset='1' and reset='0' and Hold='0' then --reset is done, start executing
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InReset <= '0';
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InReset <= '0';
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fetchEN <= '1';
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fetchEN <= '1';
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state <= FirstFetch1;
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state <= FirstFetch1;
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| Line 282... |
Line 290... |
elsif state=WaitForMemory then
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elsif state=WaitForMemory then
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state <= Execute;
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state <= Execute;
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FetchEn <= '1';
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FetchEn <= '1';
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IpAddend <= x"02";
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IpAddend <= x"02";
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SpAddend <= x"00";
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SpAddend <= x"00";
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if OpWE='0' then
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regIn(to_integer(unsigned(OpDestReg1))) <= OpDataIn(7 downto 0);
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regWE(to_integer(unsigned(OpDestReg1))) <= '1';
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if OpUseReg2='1' then
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regIn(to_integer(unsigned(OpDestReg2))) <= OpDataIn(15 downto 8);
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regWE(to_integer(unsigned(OpDestReg2))) <= '1';
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end if;
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end if;
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elsif state=WaitForAlu then
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elsif state=WaitForAlu then
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state <= Execute;
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state <= Execute;
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regIn(to_integer(unsigned(AluRegisterOut))) <= AluOut;
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regIn(to_integer(unsigned(AluRegOut))) <= AluOut;
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regWE(to_integer(unsigned(AluRegisterOut))) <= '1';
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regWE(to_integer(unsigned(AluRegOut))) <= '1';
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FetchEN <= '1';
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FetchEN <= '1';
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IPAddend <= x"02";
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IPAddend <= x"02";
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SPAddend <= x"00";
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SPAddend <= x"00";
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end if;
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end if;
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| Line 306... |
Line 322... |
regIn(REGCS) <= CSCarryOut;
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regIn(REGCS) <= CSCarryOut;
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regIn(REGSP) <= SPCarryOut; --with addend being 0, it'll just write SP to SP so it won't change, but this makes code easier for me
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regIn(REGSP) <= SPCarryOut; --with addend being 0, it'll just write SP to SP so it won't change, but this makes code easier for me
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regIn(REGSS) <= SSCarryOut;
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regIn(REGSS) <= SSCarryOut;
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regWE(REGSP) <= '1';
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regWE(REGSP) <= '1';
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regWE(REGSS) <= '1';
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regWE(REGSS) <= '1';
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OpUseReg2 <= '0';
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OpAddress <= "ZZZZZZZZZZZZZZZZ";
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OpAddress <= "ZZZZZZZZZZZZZZZZ";
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if UseAluTR='1' then
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if UseAluTR='1' then
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UseAluTR<='0';
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UseAluTR<='0';
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end if;
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end if;
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--actual decoding
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--actual decoding
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| Line 319... |
Line 336... |
regIn(to_integer(unsigned(bankreg1))) <= opimmd;
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regIn(to_integer(unsigned(bankreg1))) <= opimmd;
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regWE(to_integer(unsigned(bankreg1))) <= '1';
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regWE(to_integer(unsigned(bankreg1))) <= '1';
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when "0001" => --mov [reg],imm
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when "0001" => --mov [reg],imm
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OpAddress <= regOut(REGDS) & regOut(to_integer(unsigned(bankreg1)));
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OpAddress <= regOut(REGDS) & regOut(to_integer(unsigned(bankreg1)));
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OpWE <= '1';
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OpWE <= '1';
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OpData <= x"00" & opimmd;
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OpDataOut <= x"00" & opimmd;
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OpWW <= '0';
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OpWW <= '0';
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state <= WaitForMemory;
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state <= WaitForMemory;
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IPAddend <= x"00"; --disable all this because we have to wait a cycle to write memory
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IPAddend <= x"00"; --disable all this because we have to wait a cycle to write memory
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FetchEN <= '0';
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FetchEN <= '0';
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when "0011" => --group 3 comparisons
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when "0011" => --group 3 comparisons
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| Line 338... |
Line 355... |
FetchEN <= '0';
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FetchEN <= '0';
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IPAddend <= x"00";
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IPAddend <= x"00";
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AluOp <= "00" & opreg3; --nothing hard here, ALU does it all for us
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AluOp <= "00" & opreg3; --nothing hard here, ALU does it all for us
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AluIn1 <= regOut(to_integer(unsigned(bankreg1)));
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AluIn1 <= regOut(to_integer(unsigned(bankreg1)));
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AluIn2 <= regOut(to_integer(unsigned(bankreg2)));
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AluIn2 <= regOut(to_integer(unsigned(bankreg2)));
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AluRegisterOut <= bankreg1;
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AluRegOut <= bankreg1;
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--regIn(to_integer(unsigned(bankreg1))) <= AluOut;
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--regIn(to_integer(unsigned(bankreg1))) <= AluOut;
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--regWE(to_integer(unsigned(bankreg1))) <= '1';
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--regWE(to_integer(unsigned(bankreg1))) <= '1';
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when "0101" => --group 5
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when "0101" => --group 5
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case opreg3 is
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case opreg3 is
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when "000" => --subgroup 5-0
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when "000" => --subgroup 5-0
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case opreg2 is
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case opreg2 is
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when "000" => --push reg
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when "000" => --push reg
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SpAddend <= x"02"; --set SP to increment
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SpAddend <= x"02"; --set SP to increment
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OpAddress <= regOut(to_integer(unsigned(UsuallySS))) & regOut(REGSP);
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OpAddress <= regOut(to_integer(unsigned(UsuallySS))) & regOut(REGSP);
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OpWE <= '1';
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OpWE <= '1';
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OpData <= x"00" & regOut(to_integer(unsigned(bankreg1)));
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OpDataOut <= x"00" & regOut(to_integer(unsigned(bankreg1)));
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OpWW <= '1';
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OpWW <= '1';
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state <= WaitForMemory;
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state <= WaitForMemory;
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IPAddend <= x"00";
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IPAddend <= x"00";
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FetchEN <= '0';
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FetchEN <= '0';
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when "001" => --pop reg
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when "001" => --pop reg
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SPAddend <= x"FE"; --set SP to decrement
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SPAddend <= x"FE"; --set SP to decrement
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OpAddress <= regOut(to_integer(unsigned(UsuallySS))) & regOut(REGSP);
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OpAddress <= regOut(to_integer(unsigned(UsuallySS))) & regOut(REGSP);
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OpWE <= '0';
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OpWE <= '0';
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regIn(to_integer(unsigned(bankreg1))) <= OpData(7 downto 0);
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OpDestReg1 <= bankreg1;
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--regIn(to_integer(unsigned(bankreg1))) <= OpData(7 downto 0);
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OpWW <= '0';
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OpWW <= '0';
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state <= WaitForMemory;
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state <= WaitForMemory;
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IPAddend <= x"00";
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IPAddend <= x"00";
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FetchEN <= '0';
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FetchEN <= '0';
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when others =>
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when others =>
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