| Line 289... |
Line 289... |
state <= Execute;
|
state <= Execute;
|
elsif state=WaitForMemory then
|
elsif state=WaitForMemory then
|
state <= Execute;
|
state <= Execute;
|
FetchEn <= '1';
|
FetchEn <= '1';
|
IpAddend <= x"02";
|
IpAddend <= x"02";
|
SpAddend <= x"00";
|
--SpAddend <= x"00";
|
|
--SP can change here... really I don't *think* it can change from within Execute... so maybe that's redundant
|
|
regIn(REGSP) <= SPCarryOut; --with addend being 0, it'll just write SP to SP so it won't change, but this makes code easier for me
|
|
regIn(REGSS) <= SSCarryOut;
|
|
regWE(REGSP) <= '1';
|
|
regWE(REGSS) <= '1';
|
if OpWE='0' then
|
if OpWE='0' then
|
regIn(to_integer(unsigned(OpDestReg1))) <= OpDataIn(7 downto 0);
|
regIn(to_integer(unsigned(OpDestReg1))) <= OpDataIn(7 downto 0);
|
regWE(to_integer(unsigned(OpDestReg1))) <= '1';
|
regWE(to_integer(unsigned(OpDestReg1))) <= '1';
|
if OpUseReg2='1' then
|
if OpUseReg2='1' then
|
regIn(to_integer(unsigned(OpDestReg2))) <= OpDataIn(15 downto 8);
|
regIn(to_integer(unsigned(OpDestReg2))) <= OpDataIn(15 downto 8);
|
| Line 318... |
Line 323... |
RegWE <= (others => '0');
|
RegWE <= (others => '0');
|
regIn(REGIP) <= IPCarryOut;
|
regIn(REGIP) <= IPCarryOut;
|
regWE(REGIP) <= '1';
|
regWE(REGIP) <= '1';
|
regWE(REGCS) <= '1';
|
regWE(REGCS) <= '1';
|
regIn(REGCS) <= CSCarryOut;
|
regIn(REGCS) <= CSCarryOut;
|
regIn(REGSP) <= SPCarryOut; --with addend being 0, it'll just write SP to SP so it won't change, but this makes code easier for me
|
|
regIn(REGSS) <= SSCarryOut;
|
|
regWE(REGSP) <= '1';
|
|
regWE(REGSS) <= '1';
|
|
OpUseReg2 <= '0';
|
OpUseReg2 <= '0';
|
OpAddress <= "ZZZZZZZZZZZZZZZZ";
|
OpAddress <= "ZZZZZZZZZZZZZZZZ";
|
if UseAluTR='1' then
|
if UseAluTR='1' then
|
UseAluTR<='0';
|
UseAluTR<='0';
|
end if;
|
end if;
|
| Line 373... |
Line 374... |
state <= WaitForMemory;
|
state <= WaitForMemory;
|
IPAddend <= x"00";
|
IPAddend <= x"00";
|
FetchEN <= '0';
|
FetchEN <= '0';
|
when "001" => --pop reg
|
when "001" => --pop reg
|
SPAddend <= x"FE"; --set SP to decrement
|
SPAddend <= x"FE"; --set SP to decrement
|
OpAddress <= regOut(to_integer(unsigned(UsuallySS))) & regOut(REGSP);
|
--TODO account for carryover properties
|
|
OpAddress <= regOut(to_integer(unsigned(UsuallySS))) & std_logic_vector(unsigned(regOut(REGSP))-2); --decrement 2 here "early"
|
OpWE <= '0';
|
OpWE <= '0';
|
OpDestReg1 <= bankreg1;
|
OpDestReg1 <= bankreg1;
|
--regIn(to_integer(unsigned(bankreg1))) <= OpData(7 downto 0);
|
--regIn(to_integer(unsigned(bankreg1))) <= OpData(7 downto 0);
|
OpWW <= '0';
|
OpWW <= '0';
|
state <= WaitForMemory;
|
state <= WaitForMemory;
|
| Line 386... |
Line 388... |
when others =>
|
when others =>
|
--synthesis off
|
--synthesis off
|
report "Not implemented subgroup 5-0" severity error;
|
report "Not implemented subgroup 5-0" severity error;
|
--synthesis on
|
--synthesis on
|
end case;
|
end case;
|
|
when "001" => --mov reg, reg
|
|
regIn(to_integer(unsigned(bankreg1))) <= regOut(to_integer(unsigned(bankreg2)));
|
|
regWE(to_integer(unsigned(bankreg1))) <= '1';
|
when others =>
|
when others =>
|
--synthesis off
|
--synthesis off
|
report "Not implemented group 5" severity error;
|
report "Not implemented group 5" severity error;
|
--synthesis on
|
--synthesis on
|
end case;
|
end case;
|
