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[/] [tinycpu/] [trunk/] [src/] [fetch.vhd] - Diff between revs 21 and 22
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end fetch;
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end fetch;
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architecture Behavioral of fetch is
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architecture Behavioral of fetch is
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signal IR: std_logic_vector(15 downto 0);
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signal IR: std_logic_vector(15 downto 0);
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begin
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begin
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process(Clock, AddressIn, DataIn)
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process(Clock, AddressIn, DataIn, Enable)
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begin
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begin
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--if(rising_edge(Clock)) then
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--if(rising_edge(Clock)) then
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if(Enable='1') then
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if(Enable='1') then
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IR <= DataIn;
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IR <= DataIn;
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AddressOut <= AddressIn;
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AddressOut <= AddressIn;
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else
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else
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IR <= x"FFFF"; --avoid a latch
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AddressOut <= "ZZZZZZZZZZZZZZZZ";
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AddressOut <= "ZZZZZZZZZZZZZZZZ";
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end if;
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end if;
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--end if;
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--end if;
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end process;
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end process;
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--AddressOut <= AddressIn when Enable='1' else "ZZZZZZZZZZZZZZZZ";
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--AddressOut <= AddressIn when Enable='1' else "ZZZZZZZZZZZZZZZZ";
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