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--RAM module
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--Memory management component
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--4096*8 bit file
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--By having this separate, it should be fairly easy to add RAMs or ROMs later
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--simultaneous write/read support
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--This basically lets the CPU not have to worry about how memory "Really" works
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--16 bit or 8 bit data bus
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--currently just one RAM. 1024 byte blockram.vhd mapped as 0 - 1023
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--16 bit address bus
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--On Reset, will load a "default" RAM image
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.std_logic_arith.all;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use ieee.std_logic_unsigned.all;
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entity memory is
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entity memory is
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port(
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port(
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Address: in std_logic_vector(15 downto 0); --memory address
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Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
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Write: in std_logic; --write or read
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WriteWord: in std_logic; --if set, will write a full 16-bit word instead of a byte. Address must be aligned to 16-bit address. (bottom bit must be 0)
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UseTopBits: in std_logic; --if 1, top 8 bits of data is ignored and not written to memory
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WriteEnable: in std_logic;
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Clock: in std_logic;
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Clock: in std_logic;
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DataIn: in std_logic_vector(15 downto 0);
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DataIn: in std_logic_vector(15 downto 0);
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DataOut: out std_logic_vector(15 downto 0);
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DataOut: out std_logic_vector(15 downto 0)
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Reset: in std_logic
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-- Reset: in std_logic
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--RAM/ROM interface (RAMA is built in to here
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--RAMBDataIn: out std_logic_vector(15 downto 0);
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--RAMBDataOut: in std_logic_vector(15 downto 0);
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--RAMBAddress: out std_logic_vector(15 downto 0);
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--RAMBWriteEnable: out std_logic_vector(1 downto 0);
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);
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);
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end memory;
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end memory;
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architecture Behavioral of memory is
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architecture Behavioral of memory is
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constant BUSSIZE : integer := 8;
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type memorytype is array(0 to integer((2**BUSSIZE))) of std_logic_vector(7 downto 0);
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signal mem: memorytype;
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begin
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writemem: process(Reset,Write, Address, UseTopBits, Clock)
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component blockram
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variable addr: integer range 0 to (2**BUSSIZE)-1 := 0;
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port(
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Address: in std_logic_vector(7 downto 0); --memory address
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WriteEnable: in std_logic_vector(1 downto 0); --write or read
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Enable: in std_logic;
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Clock: in std_logic;
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DataIn: in std_logic_vector(15 downto 0);
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DataOut: out std_logic_vector(15 downto 0)
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);
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end component;
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constant R1START: integer := 0;
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constant R1END: integer := 1023;
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signal addr: std_logic_vector(15 downto 0) := (others => '0');
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signal R1addr: std_logic_vector(7 downto 0);
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signal we: std_logic_vector(1 downto 0);
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signal datawrite: std_logic_vector(15 downto 0);
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signal dataread: std_logic_vector(15 downto 0);
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--signal en: std_logic;
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signal R1we: std_logic_vector(1 downto 0);
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signal R1en: std_logic;
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signal R1in: std_logic_vector(15 downto 0);
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signal R1out: std_logic_vector(15 downto 0);
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begin
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begin
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addr := conv_integer(Address(BUSSIZE-1 downto 0));
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R1: blockram port map (R1addr, R1we, R1en, Clock, R1in, R1out);
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if(rising_edge(Clock)) then
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addrwe: process(Address, WriteWord, WriteEnable, DataIn)
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if(Reset ='1') then
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begin
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--mem <= (others => "00000000");
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addr <= Address(15 downto 1) & '0';
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elsif( Write='1') then
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if WriteEnable='1' then
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mem(addr) <= DataIn(7 downto 0);
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if WriteWord='1' then
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if(UseTopBits='1') then
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we <= "11";
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mem(addr+1) <= DataIn(15 downto 8);
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datawrite <= DataIn;
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else
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if Address(0)='0' then
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we <= "01";
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datawrite <= x"00" & DataIn(7 downto 0); --not really necessary
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else
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we <= "10";
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datawrite <= DataIn(7 downto 0) & x"00";
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end if;
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end if;
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end if;
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end if;
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else
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we <= "00";
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end if;
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end if;
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end process;
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end process;
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readmem: process(Reset,Address,Write,Clock)
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variable addr: integer range 0 to (2**BUSSIZE)-1 := 0;
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assignram: process (we, datawrite, addr, r1out)
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variable addr2: integer range 0 to (2**BUSSIZE)-1 := 0; -- for second part
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variable tmp: integer;
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variable found: boolean := false;
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begin
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begin
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addr := conv_integer(Address(BUSSIZE-1 downto 0));
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tmp := to_integer(unsigned(addr));
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addr2 := conv_integer(Address(BUSSIZE-1 downto 0));
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if tmp >= R1START and tmp <= R1END then
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if(Reset='1') then
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--map all to R1
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DataOut <= (others => '0');
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found := true;
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elsif(Write='0') then
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R1en <= '1';
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DataOut <= mem(addr+1) & mem(addr);
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R1we <= we;
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R1in <= datawrite;
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dataread <= R1out;
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R1addr <= addr(8 downto 1);
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else
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else
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DataOut <= (others => '0');
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R1en <= '0';
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R1we <= "00";
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R1in <= x"0000";
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R1addr <= x"00";
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dataread <= x"0000";
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end if;
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end if;
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end process;
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end process;
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readdata: process(Address, dataread)
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begin
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if Address(0) = '0' then
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DataOut <= dataread;
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else
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DataOut <= x"00" & dataread(15 downto 8);
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end if;
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end process;
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end Behavioral;
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end Behavioral;
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