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[/] [tinycpu/] [trunk/] [src/] [memory.vhd] - Diff between revs 37 and 38
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| Rev 37 |
Rev 38 |
| Line 79... |
Line 79... |
datawrite <= x"0000";
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datawrite <= x"0000";
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we <= "00";
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we <= "00";
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end if;
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end if;
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end process;
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end process;
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assignram: process (we, datawrite, addr, r1out, port0, WriteEnable, Address)
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assignram: process (we, datawrite, addr, r1out, port0, WriteEnable, Address, Clock)
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variable tmp: integer;
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variable tmp: integer;
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variable tmp2: integer;
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variable tmp2: integer;
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variable found: boolean := false;
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variable found: boolean := false;
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begin
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begin
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tmp := to_integer(unsigned(addr));
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tmp := to_integer(unsigned(addr));
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tmp2 := to_integer(unsigned(Address));
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tmp2 := to_integer(unsigned(Address));
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if tmp2 <= 15 then --internal registers/mapped IO
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if tmp2 <= 15 then --internal registers/mapped IO
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if rising_edge(Clock) then
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if WriteWord='0' then
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if WriteWord='0' then
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if tmp2=0 then
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if tmp2=0 then
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dataread <= x"0000";
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dataread <= x"0000";
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gen: for I in 0 to 7 loop
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gen: for I in 0 to 7 loop
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if WriteEnable='1' then
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if WriteEnable='1' then
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if port0we(I)='1' then --1-bit port set to WRITE mode
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if port0we(I)='1' then --1-bit port set to WRITE mode
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port0(I) <= DataIn(I);
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port0(I) <= DataIn(I);
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port0temp(I) <= DataIn(I);
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port0temp(I) <= DataIn(I);
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| Line 123... |
Line 125... |
else
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else
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--synthesis off
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--synthesis off
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report "Memory address is outside of bounds of RAM and registers" severity warning;
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report "Memory address is outside of bounds of RAM and registers" severity warning;
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--synthesis on
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--synthesis on
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end if;
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end if;
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else
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else
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--synthesis off
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--synthesis off
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report "WriteWord is not allowed in register area. Ignoring access" severity warning;
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report "WriteWord is not allowed in register area. Ignoring access" severity warning;
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--synthesis on
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--synthesis on
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end if;
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end if;
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end if;
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R1en <= '0';
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R1we <= "00";
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R1in <= x"0000";
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R1addr <= x"00";
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elsif tmp >= R1START and tmp <= R1END then --RAM bank1
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elsif tmp >= R1START and tmp <= R1END then --RAM bank1
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--map all to R1
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--map all to R1
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found := true;
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found := true;
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R1en <= '1';
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R1en <= '1';
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R1we <= we;
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R1we <= we;
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