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Line 1... |
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--RAM module
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--4096*8 bit file
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--simultaneous write/read support
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--16 bit or 8 bit data bus
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--16 bit address bus
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--On Reset, will load a "default" RAM image
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity memory is
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entity memory is
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port(
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port(
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Address: in std_logic_vector(15 downto 0); --memory address
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Address: in std_logic_vector(15 downto 0); --memory address
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Write: in std_logic; --write or read
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Write: in std_logic; --write or read
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UseTopBits: in std_logic; --if 1, top 8 bits of data is ignored and not written to memory
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UseTopBits: in std_logic; --if 1, top 8 bits of data is ignored and not written to memory
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| Line 28... |
Line 37... |
begin
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begin
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addr := conv_integer(Address);
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addr := conv_integer(Address);
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if(addr>size-1) then
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if(addr>size-1) then
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addr:=0;
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addr:=0;
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end if;
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end if;
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if(Reset ='1' and rising_edge(Clock)) then
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if(rising_edge(Clock)) then
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if(Reset ='1') then
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mem <= (others => "00000000");
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mem <= (others => "00000000");
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elsif(Write='1' and Reset='0') then
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elsif( Write='1') then
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if(rising_edge(clock)) then
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mem(conv_integer(addr)) <= DataIn(7 downto 0);
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mem(conv_integer(addr)) <= DataIn(7 downto 0);
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if(UseTopBits='1') then
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if(UseTopBits='1') then
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mem(conv_integer(addr)+1) <= DataIn(15 downto 8);
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mem(conv_integer(addr)+1) <= DataIn(15 downto 8);
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end if;
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end if;
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end if;
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end if;
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