OpenCores
URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] [tinycpu/] [trunk/] [src/] [memory.vhd] - Diff between revs 6 and 7

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 6 Rev 7
Line 24... Line 24...
    Reset: in std_logic
    Reset: in std_logic
  );
  );
end memory;
end memory;
 
 
architecture Behavioral of memory is
architecture Behavioral of memory is
  constant SIZE : integer := 4096;
  constant BUSSIZE : integer := 8;
  type memorytype is array(0 to (size-1)) of std_logic_vector(7 downto 0);
  type memorytype is array(0 to integer((2**BUSSIZE))) of std_logic_vector(7 downto 0);
  signal mem: memorytype;
  signal mem: memorytype;
 
 
begin
begin
 
 
  writemem: process(Reset,Write, Address, UseTopBits, Clock)
  writemem: process(Reset,Write, Address, UseTopBits, Clock)
    variable addr: integer;
    variable addr: integer range 0 to (2**BUSSIZE)-1 := 0;
  begin
  begin
    addr := conv_integer(Address);
    addr := conv_integer(Address(BUSSIZE-1 downto 0));
    if(addr>size-1) then
 
      addr:=0;
 
    end if;
 
    if(rising_edge(Clock)) then
    if(rising_edge(Clock)) then
      if(Reset ='1') then
      if(Reset ='1') then
        mem <= (others => "00000000");
        --mem <= (others => "00000000");
      elsif( Write='1') then
      elsif( Write='1') then
        mem(conv_integer(addr)) <= DataIn(7 downto 0);
        mem(addr) <= DataIn(7 downto 0);
        if(UseTopBits='1') then
        if(UseTopBits='1') then
          mem(conv_integer(addr)+1) <= DataIn(15 downto 8);
          mem(addr+1) <= DataIn(15 downto 8);
        end if;
        end if;
      end if;
      end if;
    end if;
    end if;
  end process;
  end process;
  readmem: process(Reset,Address,Write,Clock)
  readmem: process(Reset,Address,Write,Clock)
    variable addr: integer;
    variable addr: integer range 0 to (2**BUSSIZE)-1 := 0;
 
    variable addr2: integer range 0 to (2**BUSSIZE)-1 := 0; -- for second part
  begin
  begin
    addr := conv_integer(Address);
    addr := conv_integer(Address(BUSSIZE-1 downto 0));
    if(addr>size-1) then
    addr2 := conv_integer(Address(BUSSIZE-1 downto 0));
      addr:=0;
 
    end if;
 
    if(Reset='1') then
    if(Reset='1') then
      DataOut <= (others => '0');
      DataOut <= (others => '0');
    elsif(Write='0') then
    elsif(Write='0') then
      DataOut <= mem(conv_integer(addr)+1) & mem(conv_integer(addr));
      DataOut <= mem(addr+1) & mem(addr);
    else
    else
      DataOut <= (others => '0');
      DataOut <= (others => '0');
    end if;
    end if;
  end process;
  end process;
end Behavioral;
end Behavioral;
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.