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--registerfile module
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--registerfile module
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--16 registers, dual port for both read and write
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--16 registers, read/write port for all registers.
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--8 bit registers
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--8 bit registers
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.tinycpu.all;
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entity registerfile is
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entity registerfile is
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port(
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port(
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Write1:in std_logic_vector(7 downto 0); --what should be put into the write register
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WriteEnable: in regwritetype;
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Write2: in std_logic_vector(7 downto 0);
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DataIn: in regdatatype;
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SelRead1:in std_logic_vector(3 downto 0); --select which register to read
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SelRead2: in std_logic_vector(3 downto 0); --select second register to read
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SelWrite1:in std_logic_vector(3 downto 0); --select which register to write
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SelWrite2:in std_logic_vector(3 downto 0);
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UseWrite1:in std_logic; --if the register should actually be written to
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UseWrite2: in std_logic;
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Clock:in std_logic;
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Clock:in std_logic;
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Read1:out std_logic_vector(7 downto 0); --register to be read output
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DataOut: out regdatatype
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Read2:out std_logic_vector(7 downto 0) --register to be read on second output
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);
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);
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end registerfile;
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end registerfile;
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architecture Behavioral of registerfile is
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architecture Behavioral of registerfile is
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type registerstype is array(0 to 15) of std_logic_vector(7 downto 0);
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type registerstype is array(0 to 15) of std_logic_vector(7 downto 0);
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signal registers: registerstype;
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signal registers: registerstype;
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--attribute ram_style : string;
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--attribute ram_style of registers: signal is "distributed";
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begin
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begin
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writereg: process(Write1, Write2, SelWrite1, SelWrite2, UseWrite1, UseWrite2, Clock)
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regs:
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for I in 0 to 15 generate
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process(WriteEnable(I), DataIn(I), Clock)
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begin
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begin
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if(UseWrite1='1') then
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if rising_edge(Clock) then
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if(rising_edge(clock)) then
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if(WriteEnable(I) = '1') then
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registers(conv_integer(SelWrite1)) <= Write1;
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registers(I) <= DataIn(I);
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end if;
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end if;
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if(UseWrite2='1') then
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if(rising_edge(clock) and conv_integer(SelWrite1)/=conv_integer(SelWrite2)) then
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registers(conv_integer(SelWrite2)) <= Write2;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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Read1 <= registers(conv_integer(SelRead1));
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DataOut(I) <= registers(I);
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Read2 <= registers(conv_integer(SelRead2));
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end generate regs;
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end Behavioral;
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end Behavioral;
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No newline at end of file
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No newline at end of file
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