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[/] [tinycpu/] [trunk/] [src/] [registerfile.vhd] - Diff between revs 2 and 3
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity registerfile is
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entity registerfile is
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port(
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port(
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Write:in std_logic_vector(7 downto 0); --what should be put into the write register
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Write:in std_logic_vector(7 downto 0); --what should be put into the write register
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SelRead:in std_logic_vector(2 downto 0); --select which register to read
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SelRead1:in std_logic_vector(2 downto 0); --select which register to read
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SelRead2: in std_logic_vector(2 downto 0); --select second register to read
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SelWrite:in std_logic_vector(2 downto 0); --select which register to write
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SelWrite:in std_logic_vector(2 downto 0); --select which register to write
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UseWrite:in std_logic; --if the register should actually be written to
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UseWrite:in std_logic; --if the register should actually be written to
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Clock:in std_logic;
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Clock:in std_logic;
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Read:out std_logic_vector(7 downto 0) --register to be read output
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Read1:out std_logic_vector(7 downto 0); --register to be read output
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Read2:out std_logic_vector(7 downto 0) --register to be read on second output
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);
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);
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end registerfile;
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end registerfile;
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architecture Behavioral of registerfile is
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architecture Behavioral of registerfile is
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type registerstype is array(0 to 7) of std_logic_vector(7 downto 0);
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type registerstype is array(0 to 7) of std_logic_vector(7 downto 0);
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if(rising_edge(clock)) then
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if(rising_edge(clock)) then
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registers(conv_integer(SelWrite)) <= Write;
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registers(conv_integer(SelWrite)) <= Write;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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Read <= registers(conv_integer(SelRead));
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Read1 <= registers(conv_integer(SelRead1));
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Read2 <= registers(conv_integer(SelRead2));
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end Behavioral;
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end Behavioral;
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