| Line 61... |
Line 61... |
DebugCS: out std_logic_vector(7 downto 0); --current code segment
|
DebugCS: out std_logic_vector(7 downto 0); --current code segment
|
DebugTR: out std_logic; --current value of TR
|
DebugTR: out std_logic; --current value of TR
|
DebugR0: out std_logic_vector(7 downto 0)
|
DebugR0: out std_logic_vector(7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
component bootrom is
|
|
port(
|
|
CLK : in std_logic;
|
|
EN : in std_logic;
|
|
ADDR : in std_logic_vector(4 downto 0);
|
|
DATA : out std_logic_vector(15 downto 0)
|
|
);
|
|
end component;
|
signal cpuaddr: std_logic_vector(15 downto 0);
|
signal cpuaddr: std_logic_vector(15 downto 0);
|
signal cpuww: std_logic;
|
signal cpuww: std_logic;
|
signal cpuwe: std_logic;
|
signal cpuwe: std_logic;
|
signal cpumemin: std_logic_vector(15 downto 0);
|
signal cpumemin: std_logic_vector(15 downto 0);
|
signal cpumemout: std_logic_vector(15 downto 0);
|
signal cpumemout: std_logic_vector(15 downto 0);
|
| Line 76... |
Line 84... |
signal MemAddress: std_logic_vector(15 downto 0); --memory address (in bytes)
|
signal MemAddress: std_logic_vector(15 downto 0); --memory address (in bytes)
|
signal MemWriteWord: std_logic; --if set, will write a full 16-bit word instead of a byte. Address must be aligned to 16-bit address. (bottom bit must be 0)
|
signal MemWriteWord: std_logic; --if set, will write a full 16-bit word instead of a byte. Address must be aligned to 16-bit address. (bottom bit must be 0)
|
signal MemWriteEnable: std_logic;
|
signal MemWriteEnable: std_logic;
|
signal MemDataIn: std_logic_vector(15 downto 0);
|
signal MemDataIn: std_logic_vector(15 downto 0);
|
signal MemDataOut: std_logic_vector(15 downto 0);
|
signal MemDataOut: std_logic_vector(15 downto 0);
|
|
|
|
signal BootAddress: std_logic_vector(4 downto 0);
|
|
signal BootDataIn: std_logic_vector(15 downto 0);
|
|
signal BootDataOut: std_logic_vector(15 downto 0);
|
|
signal BootDone: std_logic;
|
|
constant ROMSIZE: integer := 64;
|
|
signal counter: std_logic_vector(4 downto 0);
|
begin
|
begin
|
cpu: core port map (
|
cpu: core port map (
|
MemAddr => cpuaddr,
|
MemAddr => cpuaddr,
|
MemWW => cpuww,
|
MemWW => cpuww,
|
MemWE => cpuwe,
|
MemWE => cpuwe,
|
| Line 102... |
Line 117... |
Clock => Clock,
|
Clock => Clock,
|
DataIn => MemDataIn,
|
DataIn => MemDataIn,
|
DataOut => MemDataOut,
|
DataOut => MemDataOut,
|
Port0 => Port0
|
Port0 => Port0
|
);
|
);
|
|
rom: bootrom port map(
|
MemAddress <= cpuaddr when DMA='0' else Address;
|
clk => clock,
|
MemWriteWord <= cpuww when DMA='0' else '1';
|
EN => '1',
|
MemWriteEnable <= cpuwe when DMA='0' else WriteEnable;
|
Addr => BootAddress,
|
MemDataIn <= cpumemout when DMA='0' else Data when WriteEnable='1' else "ZZZZZZZZZZZZZZZZ";
|
Data => BootDataOut
|
|
);
|
|
MemAddress <= cpuaddr when (DMA='0' and Reset='0') else "00000001000" & BootAddress when (Reset='1' and DMA='0') else Address;
|
|
MemWriteWord <= cpuww when DMA='0' and Reset='0' else '1' when Reset='1' and DMA='0' else '1';
|
|
MemWriteEnable <= cpuwe when DMA='0' and Reset='0' else'1' when Reset='1' and DMA='0' else WriteEnable;
|
|
MemDataIn <= cpumemout when DMA='0' and Reset='0' else Data when WriteEnable='1' else BootDataIn when Reset='1' and DMA='0' else "ZZZZZZZZZZZZZZZZ";
|
cpumemin <= MemDataOut;
|
cpumemin <= MemDataOut;
|
Data <= MemDataOut when DMA='1' and WriteEnable='0' else "ZZZZZZZZZZZZZZZZ";
|
Data <= MemDataOut when DMA='1' and Reset='0' and WriteEnable='0' else "ZZZZZZZZZZZZZZZZ";
|
|
|
|
bootload: process(Clock, Reset)
|
|
begin
|
|
if rising_edge(clock) then
|
|
if Reset='0' then
|
|
counter <= "00000";
|
|
BootDone <= '0';
|
|
elsif Reset='1' and BootDone='0' then
|
|
BootAddress <= counter;
|
|
BootDataIn <= BootDataOut;
|
|
counter <= std_logic_vector(unsigned(counter) + 1);
|
|
if to_integer(unsigned(counter))>=(ROMSIZE/2-1) then
|
|
BootDone <= '1';
|
|
end if;
|
|
else
|
|
|
|
end if;
|
|
end if;
|
|
end process;
|
end Behavioral;
|
end Behavioral;
|
No newline at end of file
|
No newline at end of file
|
