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Line 86... |
signal MemWriteEnable: std_logic;
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signal MemWriteEnable: std_logic;
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signal MemDataIn: std_logic_vector(15 downto 0);
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signal MemDataIn: std_logic_vector(15 downto 0);
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signal MemDataOut: std_logic_vector(15 downto 0);
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signal MemDataOut: std_logic_vector(15 downto 0);
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signal BootAddress: std_logic_vector(4 downto 0);
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signal BootAddress: std_logic_vector(4 downto 0);
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signal BootMemAddress: std_logic_vector(15 downto 0);
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signal BootDataIn: std_logic_vector(15 downto 0);
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signal BootDataIn: std_logic_vector(15 downto 0);
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signal BootDataOut: std_logic_vector(15 downto 0);
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signal BootDataOut: std_logic_vector(15 downto 0);
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signal BootDone: std_logic;
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signal BootDone: std_logic;
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signal BootFirst: std_logic;
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constant ROMSIZE: integer := 64;
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constant ROMSIZE: integer := 64;
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signal counter: std_logic_vector(4 downto 0);
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signal counter: std_logic_vector(4 downto 0);
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begin
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begin
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cpu: core port map (
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cpu: core port map (
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MemAddr => cpuaddr,
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MemAddr => cpuaddr,
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| Line 123... |
Line 125... |
clk => clock,
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clk => clock,
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EN => '1',
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EN => '1',
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Addr => BootAddress,
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Addr => BootAddress,
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Data => BootDataOut
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Data => BootDataOut
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);
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);
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MemAddress <= cpuaddr when (DMA='0' and Reset='0') else "00000001000" & BootAddress when (Reset='1' and DMA='0') else Address;
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MemAddress <= cpuaddr when (DMA='0' and Reset='0') else BootMemAddress when (Reset='1' and DMA='0') else Address;
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MemWriteWord <= cpuww when DMA='0' and Reset='0' else '1' when Reset='1' and DMA='0' else '1';
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MemWriteWord <= cpuww when DMA='0' and Reset='0' else '1' when Reset='1' and DMA='0' else '1';
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MemWriteEnable <= cpuwe when DMA='0' and Reset='0' else'1' when Reset='1' and DMA='0' else WriteEnable;
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MemWriteEnable <= cpuwe when DMA='0' and Reset='0' else'1' when Reset='1' and DMA='0' else WriteEnable;
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MemDataIn <= cpumemout when DMA='0' and Reset='0' else Data when WriteEnable='1' else BootDataIn when Reset='1' and DMA='0' else "ZZZZZZZZZZZZZZZZ";
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MemDataIn <= cpumemout when DMA='0' and Reset='0' else Data when WriteEnable='1' else BootDataIn when Reset='1' and DMA='0' else "ZZZZZZZZZZZZZZZZ";
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cpumemin <= MemDataOut;
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cpumemin <= MemDataOut;
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Data <= MemDataOut when DMA='1' and Reset='0' and WriteEnable='0' else "ZZZZZZZZZZZZZZZZ";
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Data <= MemDataOut when DMA='1' and Reset='0' and WriteEnable='0' else "ZZZZZZZZZZZZZZZZ";
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bootload: process(Clock, Reset)
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bootload: process(Clock, Reset)
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begin
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begin
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if rising_edge(clock) then
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if rising_edge(clock) then
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if Reset='0' then
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if Reset='0' then
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counter <= "00000";
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counter <= "00000";
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BootDone <= '0';
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BootDone <= '0';
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BootAddress <= "00000";
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BootDataIn <= BootDataOut;
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BootFirst <= '1';
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elsif Reset='1' and BootFirst='1' then
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BootMemAddress <= "00000001000" & "00000";
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BootAddress <= "00001";
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--BootDataIn <= BootDataOut;
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counter <= "00001";
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BootFirst <= '0';
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elsif Reset='1' and BootDone='0' then
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elsif Reset='1' and BootDone='0' then
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BootAddress <= counter;
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BootMemAddress <= "0000000100" & std_logic_vector(unsigned(counter)-1) & "0";
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BootAddress <= std_logic_vector(unsigned(counter) + 1);
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BootDataIn <= BootDataOut;
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BootDataIn <= BootDataOut;
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counter <= std_logic_vector(unsigned(counter) + 1);
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counter <= std_logic_vector(unsigned(counter) + 1);
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if to_integer(unsigned(counter))>=(ROMSIZE/2-1) then
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if to_integer(unsigned(counter))>=(ROMSIZE/2-2) then
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BootDone <= '1';
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BootDone <= '1';
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end if;
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end if;
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else
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else
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end if;
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end if;
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