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Line 9... |
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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component blockram
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component blockram
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port(
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port(
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Address: in std_logic_vector(7 downto 0); --memory address
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Address: in std_logic_vector(11 downto 0); --memory address
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WriteEnable: in std_logic; --write or read
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WriteEnable: in std_logic_vector(1 downto 0); --write or read
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Enable: in std_logic;
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Enable: in std_logic;
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Clock: in std_logic;
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Clock: in std_logic;
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DataIn: in std_logic_vector(15 downto 0);
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DataIn: in std_logic_vector(15 downto 0);
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DataOut: out std_logic_vector(15 downto 0)
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DataOut: out std_logic_vector(15 downto 0)
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);
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);
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end component;
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end component;
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--Inputs
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--Inputs
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signal Address: std_logic_vector(7 downto 0) := (others => '0');
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signal Address: std_logic_vector(11 downto 0) := (others => '0');
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signal WriteEnable: std_logic := '0';
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signal WriteEnable: std_logic_vector(1 downto 0) := (others => '0');
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signal DataIn: std_logic_vector(15 downto 0) := (others => '0');
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signal DataIn: std_logic_vector(15 downto 0) := (others => '0');
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signal Enable: std_logic := '0';
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signal Enable: std_logic := '0';
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--Outputs
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--Outputs
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signal DataOut: std_logic_vector(15 downto 0);
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signal DataOut: std_logic_vector(15 downto 0);
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wait for 100 ns;
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wait for 100 ns;
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wait for clock_period*10;
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wait for clock_period*10;
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--case 1
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--case 1
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WriteEnable <= '0';
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WriteEnable(0) <= '0';
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WriteEnable(1) <= '0';
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wait for 10 ns;
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wait for 10 ns;
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Address <= x"01";
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Address <= x"001";
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DataIn <= "1000000000001000";
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DataIn <= "1000000000001000";
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WriteEnable <= '1';
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WriteEnable(0) <= '1';
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WriteEnable(1) <= '1';
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wait for 10 ns;
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wait for 10 ns;
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WriteEnable <= '0';
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WriteEnable(0) <= '0';
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WriteEnable(1) <= '0';
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wait for 10 ns;
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wait for 10 ns;
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assert (DataOut="1000000000001000") report "Storage error case 1" severity error;
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assert (DataOut="1000000000001000") report "Storage error case 1" severity error;
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--case 2
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--case 2
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Address <= x"33";
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Address <= x"033";
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DataIn <= "1000000000001100";
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DataIn <= "1000000000001100";
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WriteEnable <= '1';
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WriteEnable(0) <= '1';
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WriteEnable(1) <= '1';
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wait for 10 ns;
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wait for 10 ns;
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WriteEnable <= '0';
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WriteEnable(0) <= '0';
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WriteEnable(1) <= '0';
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wait for 10 ns;
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wait for 10 ns;
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assert (DataOut="1000000000001100") report "memory selection error case 2" severity error;
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assert (DataOut="1000000000001100") report "memory selection error case 2" severity error;
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-- case 3
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-- case 3
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Address <= x"01";
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Address <= x"001";
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wait for 10 ns;
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wait for 10 ns;
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assert (DataOut="1000000000001000") report "memory retention error case 3" severity error;
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assert (DataOut="1000000000001000") report "memory retention error case 3" severity error;
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--case 5
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--case 5
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