| Line 15... |
Line 15... |
EnableCarry: in std_logic;
|
EnableCarry: in std_logic;
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DataIn: in std_logic_vector(7 downto 0);
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DataIn: in std_logic_vector(7 downto 0);
|
SegmentIn: in std_logic_vector(7 downto 0);
|
SegmentIn: in std_logic_vector(7 downto 0);
|
Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
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Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
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DataOut: out std_logic_vector(7 downto 0);
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DataOut: out std_logic_vector(7 downto 0);
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SegmentOut: out std_logic_vector(7 downto 0)
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SegmentOut: out std_logic_vector(7 downto 0);
|
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Clock: in std_logic
|
-- Debug: out std_logic_vector(8 downto 0)
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-- Debug: out std_logic_vector(8 downto 0)
|
);
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);
|
end component;
|
end component;
|
|
component registerfile is
|
|
port(
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|
WriteEnable: in regwritetype;
|
|
DataIn: in regdatatype;
|
|
Clock: in std_logic;
|
|
DataOut: out regdatatype
|
|
);
|
|
end component;
|
|
|
|
|
--Inputs
|
--Inputs
|
signal EnableCarry: std_logic := '0';
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signal EnableCarry: std_logic := '0';
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signal DataIn: std_logic_vector(7 downto 0) := "00000000";
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signal DataIn: std_logic_vector(7 downto 0) := "00000000";
|
| Line 31... |
Line 40... |
--Outputs
|
--Outputs
|
signal DataOut: std_logic_vector(7 downto 0);
|
signal DataOut: std_logic_vector(7 downto 0);
|
signal SegmentOut: std_logic_vector(7 downto 0);
|
signal SegmentOut: std_logic_vector(7 downto 0);
|
-- signal Debug: std_logic_vector(8 downto 0);
|
-- signal Debug: std_logic_vector(8 downto 0);
|
|
|
|
signal regwe: regwritetype;
|
|
signal regin: regdatatype;
|
|
signal regout: regdatatype;
|
|
|
signal Clock: std_logic;
|
signal Clock: std_logic;
|
constant clock_period : time := 10 ns;
|
constant clock_period : time := 10 ns;
|
|
|
BEGIN
|
BEGIN
|
|
|
| Line 43... |
Line 56... |
EnableCarry => EnableCarry,
|
EnableCarry => EnableCarry,
|
DataIn => DataIn,
|
DataIn => DataIn,
|
Addend => Addend,
|
Addend => Addend,
|
SegmentIn => SegmentIn,
|
SegmentIn => SegmentIn,
|
DataOut => DataOut,
|
DataOut => DataOut,
|
SegmentOut => SegmentOut
|
SegmentOut => SegmentOut,
|
|
Clock => Clock
|
-- Debug => Debug
|
-- Debug => Debug
|
);
|
);
|
|
regfile: registerfile port map(
|
|
WriteEnable => regwe,
|
|
DataIn => regin,
|
|
Clock => Clock,
|
|
DataOut => regout
|
|
);
|
|
|
-- Clock process definitions
|
-- Clock process definitions
|
clock_process :process
|
clock_process :process
|
begin
|
begin
|
Clock <= '0';
|
Clock <= '0';
|
| Line 97... |
Line 117... |
Addend <= x"7F";
|
Addend <= x"7F";
|
SegmentIn <= x"00";
|
SegmentIn <= x"00";
|
wait for 10 ns;
|
wait for 10 ns;
|
assert (SegmentOut=x"00" and DataOut = x"FE") report "Carryover when not appropriate case 1" severity error;
|
assert (SegmentOut=x"00" and DataOut = x"FE") report "Carryover when not appropriate case 1" severity error;
|
|
|
|
--practical register test
|
|
regin(0) <= x"10";
|
|
regwe(0) <= '1';
|
|
wait for 10 ns;
|
|
regwe(0) <= '0';
|
|
wait for 10 ns;
|
|
regwe(0) <= '1';
|
|
DataIn <= regout(0);
|
|
Addend <= x"02";
|
|
SegmentIn <= x"00";
|
|
wait for 10 ns;
|
|
regin(0) <= DataOut;
|
|
wait for 10 ns;
|
|
assert(DataOut = x"12") report "practical fail 1" severity error;
|
|
DataIn <= regout(0);
|
|
regin(0) <= DataOut;
|
|
wait for 10 ns;
|
|
assert(DataOut = x"14") report "practical fail 2" severity error;
|
|
|
-- summary of testbench
|
-- summary of testbench
|
assert false
|
assert false
|
report "Testbench of carryover completed successfully!"
|
report "Testbench of carryover completed successfully!"
|
severity note;
|
severity note;
|
|
|
