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Line 39... |
--memory interface
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--memory interface
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signal MemAddr: std_logic_vector(15 downto 0); --memory address (in bytes)
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signal MemAddr: std_logic_vector(15 downto 0); --memory address (in bytes)
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signal MemWW: std_logic; --memory writeword
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signal MemWW: std_logic; --memory writeword
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signal MemWE: std_logic; --memory writeenable
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signal MemWE: std_logic; --memory writeenable
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signal MemOut: std_logic_vector(15 downto 0);
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signal MemOut: std_logic_vector(15 downto 0);
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signal MemIn: std_logic_vector(15 downto 0);
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signal MemIn: std_logic_vector(15 downto 0):=x"0000";
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--general interface
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--general interface
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signal Reset: std_logic; --When this is high, CPU will reset within 1 clock cycles.
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signal Reset: std_logic:='0'; --When this is high, CPU will reset within 1 clock cycles.
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--Enable: in std_logic; --When this is high, the CPU executes as normal, when low the CPU stops at the next clock cycle(maintaining all state)
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--Enable: in std_logic; --When this is high, the CPU executes as normal, when low the CPU stops at the next clock cycle(maintaining all state)
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signal Hold: std_logic; --when high, CPU pauses execution and places Memory interfaces into high impendance state so the memory can be used by other components
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signal Hold: std_logic:='0'; --when high, CPU pauses execution and places Memory interfaces into high impendance state so the memory can be used by other components
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signal HoldAck: std_logic; --when high, CPU acknowledged hold and buses are in high Z
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signal HoldAck: std_logic; --when high, CPU acknowledged hold and buses are in high Z
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--todo: port interface
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--todo: port interface
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--debug ports:
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--debug ports:
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signal DebugIR: std_logic_vector(15 downto 0); --current instruction
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signal DebugIR: std_logic_vector(15 downto 0); --current instruction
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Line 109... |
wait for 10 ns;
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wait for 10 ns;
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assert(HoldAck = '0') report "hold state lasts longer than it should" severity error;
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assert(HoldAck = '0') report "hold state lasts longer than it should" severity error;
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Reset <= '0';
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Reset <= '0';
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MemIn <= x"0012"; --mov r0, 0xFF
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MemIn <= x"0012"; --mov r0, 0xFF
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wait for 10 ns;
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wait for 30 ns; --fetcher needs two clock cycles to catch up
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assert(MemAddr = x"0100") report "Not fetching from correct start address" severity error;
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assert(MemAddr = x"0100") report "Not fetching from correct start address" severity error;
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MemIn <= x"00F1"; --mov r0, 0xF1
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MemIn <= x"00F1"; --mov r0, 0xF1
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wait for 10 ns;
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wait for 10 ns;
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assert(MemAddr = x"0102") report "fetcher is not incrementing address" severity error;
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assert(MemAddr = x"0102") report "fetcher is not incrementing address" severity error;
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assert(DebugIR = x"00F1" and DebugR0 /= x"12") report "IR is not correct. Execution occurs during first fetch";
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assert(DebugIR = x"00F1" and DebugR0 /= x"12") report "IR is not correct. Execution occurs during first fetch";
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