| Line 109... |
Line 109... |
wait for 10 ns;
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wait for 10 ns;
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assert(HoldAck = '0') report "hold state lasts longer than it should" severity error;
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assert(HoldAck = '0') report "hold state lasts longer than it should" severity error;
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Reset <= '0';
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Reset <= '0';
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MemIn <= x"0012"; --mov r0, 0xFF
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MemIn <= x"0012"; --mov r0, 0xFF
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wait for 30 ns; --fetcher needs two clock cycles to catch up
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wait for 20 ns; --fetcher needs two clock cycles to catch up
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assert(MemAddr = x"0100") report "Not fetching from correct start address" severity error;
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assert(MemAddr = x"0100") report "Not fetching from correct start address" severity error;
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MemIn <= x"00F1"; --mov r0, 0xF1
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MemIn <= x"00F1"; --mov r0, 0xF1
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wait for 10 ns;
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wait for 10 ns;
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assert(MemAddr = x"0102") report "fetcher is not incrementing address" severity error;
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assert(MemAddr = x"0102") report "fetcher is not incrementing address" severity error;
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assert(DebugIR = x"00F1" and DebugR0 /= x"12") report "IR is not correct. Execution occurs during first fetch";
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assert(DebugIR = x"00F1" and DebugR0 /= x"12") report "IR is not correct. Execution occurs during first fetch";
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MemIn <= x"0056";
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MemIn <= x"0056";
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wait for 10 ns;
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wait for 10 ns;
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assert(DebugR0 = x"F1") report "loaded value of R0 is not correct" severity error;
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assert(DebugR0 = x"F1") report "loaded value of R0 is not correct" severity error;
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MemIn <= x"0E50"; --mov IP, 0x50
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wait for 10 ns;
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wait for 10 ns;
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assert( MemAddr = x"0150") report "mov to IP doesn't work" severity error; --DebugIP uses regOut, so it won't be updated until next clock cycle actually, but it's correct.
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MemIn <= x"0020"; --mov r0, 0x20
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wait for 10 ns;
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assert (MemAddr = x"0152" and DebugIP=x"50") report "fetching is wrong after move to IP" severity error; --DebugIP uses regOut, Fetchaddress uses regIn, so this is correct
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wait for 10 ns; --wait until register write happens
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assert(DebugR0 = x"20") report "mov to r0 is wrong after move to IP" severity error;
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-- summary of testbench
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-- summary of testbench
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assert false
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assert false
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report "Testbench of core completed successfully!"
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report "Testbench of core completed successfully!"
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severity note;
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severity note;
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