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[/] [tinycpu/] [trunk/] [testbench/] [core_tb.vhd] - Diff between revs 25 and 26
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| Rev 25 |
Rev 26 |
| Line 129... |
Line 129... |
MemIn <= x"0160"; --mov r0,0x60 if TR is set
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MemIn <= x"0160"; --mov r0,0x60 if TR is set
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wait for 10 ns; --wait until register write happens
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wait for 10 ns; --wait until register write happens
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assert(DebugR0 = x"20") report "mov to r0 is wrong after move to IP" severity error;
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assert(DebugR0 = x"20") report "mov to r0 is wrong after move to IP" severity error;
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MemIn <= x"1050"; --mov [r0], 0x50 (r0 is 0x20)
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MemIn <= x"1050"; --mov [r0], 0x50 (r0 is 0x20)
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wait for 10 ns;
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wait for 10 ns;
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MemIn <= x"0025"; --mov r0,0x25
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assert(DebugR0 = x"20" and DebugTR='0') report "moved to r0 conditional thought TR is 0" severity error;
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assert(DebugR0 = x"20" and DebugTR='0') report "moved to r0 conditional thought TR is 0" severity error;
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wait for 10 ns;
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wait for 10 ns; --wait for memory
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assert(MemAddr = x"0020" and MemWE='1' and MemWW='0' and MemOut=x"0050") report "Write to memory doesn't work" severity error;
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assert(MemAddr = x"0020" and MemWE='1' and MemWW='0' and MemOut=x"0050") report "Write to memory doesn't work" severity error;
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wait for 10 ns;
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wait for 10 ns;
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--wait for 10 ns; --have to wait an extra cycle for memory
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--wait for 10 ns; --have to wait an extra cycle for memory
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-- summary of testbench
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-- summary of testbench
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