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[/] [tinycpu/] [trunk/] [testbench/] [core_tb.vhd] - Diff between revs 26 and 27
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| Rev 26 |
Rev 27 |
| Line 132... |
Line 132... |
MemIn <= x"1050"; --mov [r0], 0x50 (r0 is 0x20)
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MemIn <= x"1050"; --mov [r0], 0x50 (r0 is 0x20)
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wait for 10 ns;
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wait for 10 ns;
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MemIn <= x"0025"; --mov r0,0x25
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MemIn <= x"0025"; --mov r0,0x25
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assert(DebugR0 = x"20" and DebugTR='0') report "moved to r0 conditional thought TR is 0" severity error;
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assert(DebugR0 = x"20" and DebugTR='0') report "moved to r0 conditional thought TR is 0" severity error;
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assert(MemAddr = x"0020" and MemWE='1' and MemWW='0' and MemOut=x"0050") report "Write to memory doesn't work" severity error;
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assert(MemAddr = x"0020" and MemWE='1' and MemWW='0' and MemOut=x"0050") report "Write to memory doesn't work" severity error;
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wait for 20 ns; --wait an extra cycle because of WaitForMemory state
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MemIn <= x"0235"; --mov r1,0x35
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wait for 10 ns;
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wait for 10 ns;
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MemIn <= "0011000000010000"; --compare greater than r0, r1 : TR=r0 > r1
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wait for 10 ns;
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assert(DebugTR ='0') report "ALU compare is not correct for greater than" severity error;
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MemIn <= "0011000000010010"; --TR=r0 < r1
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wait for 20 ns;
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assert(DebugTR='1') report "ALU compare is not correct for less than" severity error;
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--wait for 10 ns; --have to wait an extra cycle for memory
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--wait for 10 ns; --have to wait an extra cycle for memory
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-- summary of testbench
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-- summary of testbench
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assert false
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assert false
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report "Testbench of core completed successfully!"
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report "Testbench of core completed successfully!"
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