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https://opencores.org/ocsvn/tinycpu/tinycpu/trunk
[/] [tinycpu/] [trunk/] [testbench/] [memory_tb.vhd] - Diff between revs 37 and 41
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Rev 37 |
Rev 41 |
Line 118... |
Line 118... |
WriteEnable <= '0';
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WriteEnable <= '0';
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wait for 10 ns;
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wait for 10 ns;
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assert (DataOut = x"5678") report "aligned 8-bit memory write is wrong" severity error;
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assert (DataOut = x"5678") report "aligned 8-bit memory write is wrong" severity error;
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Address <= x"0001";
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Address <= x"0001";
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Port0 <= "ZZZZZZ1Z";
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WriteWord<='0';
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WriteEnable <= '1';
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DataIn <= x"0001";
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wait for 10 ns;
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WriteEnable <= '0';
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Address <= x"1234";
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wait for 20 ns;
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WriteEnable <= '1';
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Address <= x"0000";
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DataIn <= x"0001";
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wait for 10 ns;
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WriteEnable <= '0';
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assert(Port0(0)='1') report "port0 not right 1" severity error;
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wait for 10 ns;
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assert(DataOut(1)='1') report "port0 not right 2" severity error;
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wait for 10 ns;
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Address <= x"0001";
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WriteWord <= '0';
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WriteWord <= '0';
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WriteEnable <= '1';
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WriteEnable <= '1';
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DataIn <= b"00000000_0011_1000";
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DataIn <= b"00000000_0011_1000";
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wait for 10 ns;
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wait for 10 ns;
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Address <= x"0000";
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Address <= x"0000";
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